Home
last modified time | relevance | path

Searched refs:has_initial_ (Results 1 – 2 of 2) sorted by relevance

/dports/cad/iverilog/verilog-11.0/tgt-vhdl/
H A Dvhdl_syntax.hh608 has_initial_(initial != NULL) {} in vhdl_decl()
615 bool has_initial() const { return has_initial_; } in has_initial()
643 bool has_initial_; member in vhdl_decl
H A Dvhdl_syntax.cc444 if (!has_initial_) { in set_initial()
447 has_initial_ = true; in set_initial()