| /dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 86 u32 hclk_div; in rkclk_init() local
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
141 hclk_div << BUS_HCLK_DIV_SHIFT); in rkclk_init()
150 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
151 assert((1 << hclk_div) * PERI_HCLK_HZ == in rkclk_init()
152 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
163 hclk_div << PERI_HCLK_DIV_SHIFT | in rkclk_init()
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 81 u32 hclk_div; in rkclk_init() local
125 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
126 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
136 hclk_div << BUS_HCLK_DIV_SHIFT); in rkclk_init()
145 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
146 assert((1 << hclk_div) * PERI_HCLK_HZ == in rkclk_init()
147 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
158 hclk_div << PERI_HCLK_DIV_SHIFT | in rkclk_init()
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 81 u32 hclk_div; in rkclk_init() local
125 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
126 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
136 hclk_div << BUS_HCLK_DIV_SHIFT); in rkclk_init()
145 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
146 assert((1 << hclk_div) * PERI_HCLK_HZ == in rkclk_init()
147 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
158 hclk_div << PERI_HCLK_DIV_SHIFT | in rkclk_init()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 86 u32 hclk_div; in rkclk_init() local
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
141 hclk_div << BUS_HCLK_DIV_SHIFT); in rkclk_init()
150 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
151 assert((1 << hclk_div) * PERI_HCLK_HZ == in rkclk_init()
152 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
163 hclk_div << PERI_HCLK_DIV_SHIFT | in rkclk_init()
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 86 u32 hclk_div; in rkclk_init() local
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
141 hclk_div << BUS_HCLK_DIV_SHIFT); in rkclk_init()
150 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
151 assert((1 << hclk_div) * PERI_HCLK_HZ == in rkclk_init()
152 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
163 hclk_div << PERI_HCLK_DIV_SHIFT | in rkclk_init()
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 86 u32 hclk_div; in rkclk_init() local
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
141 hclk_div << BUS_HCLK_DIV_SHIFT); in rkclk_init()
150 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
151 assert((1 << hclk_div) * PERI_HCLK_HZ == in rkclk_init()
152 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
163 hclk_div << PERI_HCLK_DIV_SHIFT | in rkclk_init()
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 86 u32 hclk_div; in rkclk_init() local
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
141 hclk_div << BUS_HCLK_DIV_SHIFT); in rkclk_init()
150 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
151 assert((1 << hclk_div) * PERI_HCLK_HZ == in rkclk_init()
152 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
163 hclk_div << PERI_HCLK_DIV_SHIFT | in rkclk_init()
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 81 u32 hclk_div; in rkclk_init() local
125 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
126 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
136 hclk_div << BUS_HCLK_DIV_SHIFT); in rkclk_init()
145 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
146 assert((1 << hclk_div) * PERI_HCLK_HZ == in rkclk_init()
147 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
158 hclk_div << PERI_HCLK_DIV_SHIFT | in rkclk_init()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 86 u32 hclk_div; in rkclk_init() local
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
141 hclk_div << BUS_HCLK_DIV_SHIFT); in rkclk_init()
150 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
151 assert((1 << hclk_div) * PERI_HCLK_HZ == in rkclk_init()
152 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
163 hclk_div << PERI_HCLK_DIV_SHIFT | in rkclk_init()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 86 u32 hclk_div; in rkclk_init() local
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
141 hclk_div << BUS_HCLK_DIV_SHIFT); in rkclk_init()
150 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
151 assert((1 << hclk_div) * PERI_HCLK_HZ == in rkclk_init()
152 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
163 hclk_div << PERI_HCLK_DIV_SHIFT | in rkclk_init()
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 86 u32 hclk_div; in rkclk_init() local
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
141 hclk_div << BUS_HCLK_DIV_SHIFT); in rkclk_init()
150 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
151 assert((1 << hclk_div) * PERI_HCLK_HZ == in rkclk_init()
152 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
163 hclk_div << PERI_HCLK_DIV_SHIFT | in rkclk_init()
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 86 u32 hclk_div; in rkclk_init() local
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
141 hclk_div << BUS_HCLK_DIV_SHIFT); in rkclk_init()
150 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
151 assert((1 << hclk_div) * PERI_HCLK_HZ == in rkclk_init()
152 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
163 hclk_div << PERI_HCLK_DIV_SHIFT | in rkclk_init()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 86 u32 hclk_div; in rkclk_init() local
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
141 hclk_div << BUS_HCLK_DIV_SHIFT); in rkclk_init()
150 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
151 assert((1 << hclk_div) * PERI_HCLK_HZ == in rkclk_init()
152 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
163 hclk_div << PERI_HCLK_DIV_SHIFT | in rkclk_init()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 86 u32 hclk_div; in rkclk_init() local
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
141 hclk_div << BUS_HCLK_DIV_SHIFT); in rkclk_init()
150 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
151 assert((1 << hclk_div) * PERI_HCLK_HZ == in rkclk_init()
152 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
163 hclk_div << PERI_HCLK_DIV_SHIFT | in rkclk_init()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 86 u32 hclk_div; in rkclk_init() local
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
141 hclk_div << BUS_HCLK_DIV_SHIFT); in rkclk_init()
150 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
151 assert((1 << hclk_div) * PERI_HCLK_HZ == in rkclk_init()
152 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
163 hclk_div << PERI_HCLK_DIV_SHIFT | in rkclk_init()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 86 u32 hclk_div; in rkclk_init() local
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
141 hclk_div << BUS_HCLK_DIV_SHIFT); in rkclk_init()
150 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
151 assert((1 << hclk_div) * PERI_HCLK_HZ == in rkclk_init()
152 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
163 hclk_div << PERI_HCLK_DIV_SHIFT | in rkclk_init()
|
| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 86 u32 hclk_div; in rkclk_init() local
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
141 hclk_div << BUS_HCLK_DIV_SHIFT); in rkclk_init()
150 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
151 assert((1 << hclk_div) * PERI_HCLK_HZ == in rkclk_init()
152 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
163 hclk_div << PERI_HCLK_DIV_SHIFT | in rkclk_init()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 86 u32 hclk_div; in rkclk_init() local
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
141 hclk_div << BUS_HCLK_DIV_SHIFT); in rkclk_init()
150 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
151 assert((1 << hclk_div) * PERI_HCLK_HZ == in rkclk_init()
152 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
163 hclk_div << PERI_HCLK_DIV_SHIFT | in rkclk_init()
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 86 u32 hclk_div; in rkclk_init() local
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
141 hclk_div << BUS_HCLK_DIV_SHIFT); in rkclk_init()
150 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
151 assert((1 << hclk_div) * PERI_HCLK_HZ == in rkclk_init()
152 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
163 hclk_div << PERI_HCLK_DIV_SHIFT | in rkclk_init()
|
| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 86 u32 hclk_div; in rkclk_init() local
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
141 hclk_div << BUS_HCLK_DIV_SHIFT); in rkclk_init()
150 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
151 assert((1 << hclk_div) * PERI_HCLK_HZ == in rkclk_init()
152 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
163 hclk_div << PERI_HCLK_DIV_SHIFT | in rkclk_init()
|
| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 86 u32 hclk_div; in rkclk_init() local
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
141 hclk_div << BUS_HCLK_DIV_SHIFT); in rkclk_init()
150 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
151 assert((1 << hclk_div) * PERI_HCLK_HZ == in rkclk_init()
152 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
163 hclk_div << PERI_HCLK_DIV_SHIFT | in rkclk_init()
|
| /dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 86 u32 hclk_div; in rkclk_init() local
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
141 hclk_div << BUS_HCLK_DIV_SHIFT); in rkclk_init()
150 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
151 assert((1 << hclk_div) * PERI_HCLK_HZ == in rkclk_init()
152 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
163 hclk_div << PERI_HCLK_DIV_SHIFT | in rkclk_init()
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 86 u32 hclk_div; in rkclk_init() local
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
141 hclk_div << BUS_HCLK_DIV_SHIFT); in rkclk_init()
150 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
151 assert((1 << hclk_div) * PERI_HCLK_HZ == in rkclk_init()
152 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
163 hclk_div << PERI_HCLK_DIV_SHIFT | in rkclk_init()
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 81 u32 hclk_div; in rkclk_init() local
125 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
126 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
136 hclk_div << BUS_HCLK_DIV_SHIFT); in rkclk_init()
145 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
146 assert((1 << hclk_div) * PERI_HCLK_HZ == in rkclk_init()
147 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
158 hclk_div << PERI_HCLK_DIV_SHIFT | in rkclk_init()
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 86 u32 hclk_div; in rkclk_init() local
130 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()
131 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
141 hclk_div << BUS_HCLK_DIV_SHIFT); in rkclk_init()
150 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); in rkclk_init()
151 assert((1 << hclk_div) * PERI_HCLK_HZ == in rkclk_init()
152 PERI_ACLK_HZ && (hclk_div < 0x4)); in rkclk_init()
163 hclk_div << PERI_HCLK_DIV_SHIFT | in rkclk_init()
|