| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 33 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
1141 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps) in get_target_freq() argument
1209 *hclk_ps = 0; in get_target_freq()
1214 *hclk_ps = 1000000 / hclk; /* values are 1/HCLK in ps */ in get_target_freq()
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| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 33 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
1141 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps) in get_target_freq() argument
1209 *hclk_ps = 0; in get_target_freq()
1214 *hclk_ps = 1000000 / hclk; /* values are 1/HCLK in ps */ in get_target_freq()
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| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 35 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
1139 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps) in get_target_freq() argument
1207 *hclk_ps = 0; in get_target_freq()
1212 *hclk_ps = 1000000 / hclk; /* values are 1/HCLK in ps */ in get_target_freq()
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| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 35 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
1139 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps) in get_target_freq() argument
1207 *hclk_ps = 0; in get_target_freq()
1212 *hclk_ps = 1000000 / hclk; /* values are 1/HCLK in ps */ in get_target_freq()
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 35 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
1139 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps) in get_target_freq() argument
1207 *hclk_ps = 0; in get_target_freq()
1212 *hclk_ps = 1000000 / hclk; /* values are 1/HCLK in ps */ in get_target_freq()
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 35 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
1139 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps) in get_target_freq() argument
1207 *hclk_ps = 0; in get_target_freq()
1212 *hclk_ps = 1000000 / hclk; /* values are 1/HCLK in ps */ in get_target_freq()
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 33 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
1141 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps) in get_target_freq() argument
1209 *hclk_ps = 0; in get_target_freq()
1214 *hclk_ps = 1000000 / hclk; /* values are 1/HCLK in ps */ in get_target_freq()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 35 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
1139 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps) in get_target_freq() argument
1207 *hclk_ps = 0; in get_target_freq()
1212 *hclk_ps = 1000000 / hclk; /* values are 1/HCLK in ps */ in get_target_freq()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 35 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
1139 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps) in get_target_freq() argument
1207 *hclk_ps = 0; in get_target_freq()
1212 *hclk_ps = 1000000 / hclk; /* values are 1/HCLK in ps */ in get_target_freq()
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 35 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
1139 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps) in get_target_freq() argument
1207 *hclk_ps = 0; in get_target_freq()
1212 *hclk_ps = 1000000 / hclk; /* values are 1/HCLK in ps */ in get_target_freq()
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 35 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
1139 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps) in get_target_freq() argument
1207 *hclk_ps = 0; in get_target_freq()
1212 *hclk_ps = 1000000 / hclk; /* values are 1/HCLK in ps */ in get_target_freq()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 35 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
1139 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps) in get_target_freq() argument
1207 *hclk_ps = 0; in get_target_freq()
1212 *hclk_ps = 1000000 / hclk; /* values are 1/HCLK in ps */ in get_target_freq()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 35 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
1139 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps) in get_target_freq() argument
1207 *hclk_ps = 0; in get_target_freq()
1212 *hclk_ps = 1000000 / hclk; /* values are 1/HCLK in ps */ in get_target_freq()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 35 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
1139 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps) in get_target_freq() argument
1207 *hclk_ps = 0; in get_target_freq()
1212 *hclk_ps = 1000000 / hclk; /* values are 1/HCLK in ps */ in get_target_freq()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 35 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
1139 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps) in get_target_freq() argument
1207 *hclk_ps = 0; in get_target_freq()
1212 *hclk_ps = 1000000 / hclk; /* values are 1/HCLK in ps */ in get_target_freq()
|
| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 35 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
1139 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps) in get_target_freq() argument
1207 *hclk_ps = 0; in get_target_freq()
1212 *hclk_ps = 1000000 / hclk; /* values are 1/HCLK in ps */ in get_target_freq()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 35 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
1139 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps) in get_target_freq() argument
1207 *hclk_ps = 0; in get_target_freq()
1212 *hclk_ps = 1000000 / hclk; /* values are 1/HCLK in ps */ in get_target_freq()
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 35 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
1139 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps) in get_target_freq() argument
1207 *hclk_ps = 0; in get_target_freq()
1212 *hclk_ps = 1000000 / hclk; /* values are 1/HCLK in ps */ in get_target_freq()
|
| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 35 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
1139 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps) in get_target_freq() argument
1207 *hclk_ps = 0; in get_target_freq()
1212 *hclk_ps = 1000000 / hclk; /* values are 1/HCLK in ps */ in get_target_freq()
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 35 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
1139 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps) in get_target_freq() argument
1207 *hclk_ps = 0; in get_target_freq()
1212 *hclk_ps = 1000000 / hclk; /* values are 1/HCLK in ps */ in get_target_freq()
|
| /dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 35 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
1139 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps) in get_target_freq() argument
1207 *hclk_ps = 0; in get_target_freq()
1212 *hclk_ps = 1000000 / hclk; /* values are 1/HCLK in ps */ in get_target_freq()
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 33 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
1141 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps) in get_target_freq() argument
1209 *hclk_ps = 0; in get_target_freq()
1214 *hclk_ps = 1000000 / hclk; /* values are 1/HCLK in ps */ in get_target_freq()
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 35 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
1139 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps) in get_target_freq() argument
1207 *hclk_ps = 0; in get_target_freq()
1212 *hclk_ps = 1000000 / hclk; /* values are 1/HCLK in ps */ in get_target_freq()
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 35 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
1139 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps) in get_target_freq() argument
1207 *hclk_ps = 0; in get_target_freq()
1212 *hclk_ps = 1000000 / hclk; /* values are 1/HCLK in ps */ in get_target_freq()
|
| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 35 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
1139 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps) in get_target_freq() argument
1207 *hclk_ps = 0; in get_target_freq()
1212 *hclk_ps = 1000000 / hclk; /* values are 1/HCLK in ps */ in get_target_freq()
|