| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/phy/ |
| H A D | phy-core-mipi-dphy.c | 24 unsigned long long hs_clk_rate; in phy_mipi_dphy_get_default_config() local
30 hs_clk_rate = pixel_clock * bpp; in phy_mipi_dphy_get_default_config()
31 do_div(hs_clk_rate, lanes); in phy_mipi_dphy_get_default_config()
33 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); in phy_mipi_dphy_get_default_config()
34 do_div(ui, hs_clk_rate); in phy_mipi_dphy_get_default_config()
72 cfg->hs_clk_rate = hs_clk_rate; in phy_mipi_dphy_get_default_config()
89 ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
90 do_div(ui, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
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| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/phy/ |
| H A D | phy-core-mipi-dphy.c | 24 unsigned long long hs_clk_rate; in phy_mipi_dphy_get_default_config() local
30 hs_clk_rate = pixel_clock * bpp; in phy_mipi_dphy_get_default_config()
31 do_div(hs_clk_rate, lanes); in phy_mipi_dphy_get_default_config()
33 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); in phy_mipi_dphy_get_default_config()
34 do_div(ui, hs_clk_rate); in phy_mipi_dphy_get_default_config()
72 cfg->hs_clk_rate = hs_clk_rate; in phy_mipi_dphy_get_default_config()
89 ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
90 do_div(ui, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
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| /dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/phy/ |
| H A D | phy-core-mipi-dphy.c | 25 unsigned long long hs_clk_rate; in phy_mipi_dphy_get_default_config() local
31 hs_clk_rate = pixel_clock * bpp; in phy_mipi_dphy_get_default_config()
32 do_div(hs_clk_rate, lanes); in phy_mipi_dphy_get_default_config()
34 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); in phy_mipi_dphy_get_default_config()
35 do_div(ui, hs_clk_rate); in phy_mipi_dphy_get_default_config()
73 cfg->hs_clk_rate = hs_clk_rate; in phy_mipi_dphy_get_default_config()
91 ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
92 do_div(ui, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
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| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/phy/ |
| H A D | phy-core-mipi-dphy.c | 24 unsigned long long hs_clk_rate; in phy_mipi_dphy_get_default_config() local
30 hs_clk_rate = pixel_clock * bpp; in phy_mipi_dphy_get_default_config()
31 do_div(hs_clk_rate, lanes); in phy_mipi_dphy_get_default_config()
33 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); in phy_mipi_dphy_get_default_config()
34 do_div(ui, hs_clk_rate); in phy_mipi_dphy_get_default_config()
72 cfg->hs_clk_rate = hs_clk_rate; in phy_mipi_dphy_get_default_config()
89 ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
90 do_div(ui, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
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| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/phy/ |
| H A D | phy-core-mipi-dphy.c | 24 unsigned long long hs_clk_rate; in phy_mipi_dphy_get_default_config() local
30 hs_clk_rate = pixel_clock * bpp; in phy_mipi_dphy_get_default_config()
31 do_div(hs_clk_rate, lanes); in phy_mipi_dphy_get_default_config()
33 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); in phy_mipi_dphy_get_default_config()
34 do_div(ui, hs_clk_rate); in phy_mipi_dphy_get_default_config()
72 cfg->hs_clk_rate = hs_clk_rate; in phy_mipi_dphy_get_default_config()
89 ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
90 do_div(ui, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
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| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/phy/ |
| H A D | phy-core-mipi-dphy.c | 24 unsigned long long hs_clk_rate; in phy_mipi_dphy_get_default_config() local
30 hs_clk_rate = pixel_clock * bpp; in phy_mipi_dphy_get_default_config()
31 do_div(hs_clk_rate, lanes); in phy_mipi_dphy_get_default_config()
33 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); in phy_mipi_dphy_get_default_config()
34 do_div(ui, hs_clk_rate); in phy_mipi_dphy_get_default_config()
72 cfg->hs_clk_rate = hs_clk_rate; in phy_mipi_dphy_get_default_config()
89 ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
90 do_div(ui, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
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| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/phy/ |
| H A D | phy-core-mipi-dphy.c | 24 unsigned long long hs_clk_rate; in phy_mipi_dphy_get_default_config() local
30 hs_clk_rate = pixel_clock * bpp; in phy_mipi_dphy_get_default_config()
31 do_div(hs_clk_rate, lanes); in phy_mipi_dphy_get_default_config()
33 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); in phy_mipi_dphy_get_default_config()
34 do_div(ui, hs_clk_rate); in phy_mipi_dphy_get_default_config()
72 cfg->hs_clk_rate = hs_clk_rate; in phy_mipi_dphy_get_default_config()
89 ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
90 do_div(ui, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
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| /dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/phy/ |
| H A D | phy-core-mipi-dphy.c | 25 unsigned long long hs_clk_rate; in phy_mipi_dphy_get_default_config() local
31 hs_clk_rate = pixel_clock * bpp; in phy_mipi_dphy_get_default_config()
32 do_div(hs_clk_rate, lanes); in phy_mipi_dphy_get_default_config()
34 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); in phy_mipi_dphy_get_default_config()
35 do_div(ui, hs_clk_rate); in phy_mipi_dphy_get_default_config()
73 cfg->hs_clk_rate = hs_clk_rate; in phy_mipi_dphy_get_default_config()
91 ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
92 do_div(ui, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
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| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/phy/ |
| H A D | phy-core-mipi-dphy.c | 24 unsigned long long hs_clk_rate; in phy_mipi_dphy_get_default_config() local
30 hs_clk_rate = pixel_clock * bpp; in phy_mipi_dphy_get_default_config()
31 do_div(hs_clk_rate, lanes); in phy_mipi_dphy_get_default_config()
33 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); in phy_mipi_dphy_get_default_config()
34 do_div(ui, hs_clk_rate); in phy_mipi_dphy_get_default_config()
72 cfg->hs_clk_rate = hs_clk_rate; in phy_mipi_dphy_get_default_config()
89 ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
90 do_div(ui, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
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| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/phy/ |
| H A D | phy-core-mipi-dphy.c | 24 unsigned long long hs_clk_rate; in phy_mipi_dphy_get_default_config() local
30 hs_clk_rate = pixel_clock * bpp; in phy_mipi_dphy_get_default_config()
31 do_div(hs_clk_rate, lanes); in phy_mipi_dphy_get_default_config()
33 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); in phy_mipi_dphy_get_default_config()
34 do_div(ui, hs_clk_rate); in phy_mipi_dphy_get_default_config()
72 cfg->hs_clk_rate = hs_clk_rate; in phy_mipi_dphy_get_default_config()
89 ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
90 do_div(ui, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/phy/ |
| H A D | phy-core-mipi-dphy.c | 24 unsigned long long hs_clk_rate; in phy_mipi_dphy_get_default_config() local
30 hs_clk_rate = pixel_clock * bpp; in phy_mipi_dphy_get_default_config()
31 do_div(hs_clk_rate, lanes); in phy_mipi_dphy_get_default_config()
33 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); in phy_mipi_dphy_get_default_config()
34 do_div(ui, hs_clk_rate); in phy_mipi_dphy_get_default_config()
72 cfg->hs_clk_rate = hs_clk_rate; in phy_mipi_dphy_get_default_config()
89 ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
90 do_div(ui, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
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| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/phy/ |
| H A D | phy-core-mipi-dphy.c | 24 unsigned long long hs_clk_rate; in phy_mipi_dphy_get_default_config() local
30 hs_clk_rate = pixel_clock * bpp; in phy_mipi_dphy_get_default_config()
31 do_div(hs_clk_rate, lanes); in phy_mipi_dphy_get_default_config()
33 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); in phy_mipi_dphy_get_default_config()
34 do_div(ui, hs_clk_rate); in phy_mipi_dphy_get_default_config()
72 cfg->hs_clk_rate = hs_clk_rate; in phy_mipi_dphy_get_default_config()
89 ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
90 do_div(ui, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
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| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/phy/ |
| H A D | phy-core-mipi-dphy.c | 24 unsigned long long hs_clk_rate; in phy_mipi_dphy_get_default_config() local
30 hs_clk_rate = pixel_clock * bpp; in phy_mipi_dphy_get_default_config()
31 do_div(hs_clk_rate, lanes); in phy_mipi_dphy_get_default_config()
33 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); in phy_mipi_dphy_get_default_config()
34 do_div(ui, hs_clk_rate); in phy_mipi_dphy_get_default_config()
72 cfg->hs_clk_rate = hs_clk_rate; in phy_mipi_dphy_get_default_config()
89 ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
90 do_div(ui, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
|
| /dports/multimedia/libv4l/linux-5.13-rc2/drivers/phy/ |
| H A D | phy-core-mipi-dphy.c | 25 unsigned long long hs_clk_rate; in phy_mipi_dphy_get_default_config() local
31 hs_clk_rate = pixel_clock * bpp; in phy_mipi_dphy_get_default_config()
32 do_div(hs_clk_rate, lanes); in phy_mipi_dphy_get_default_config()
34 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); in phy_mipi_dphy_get_default_config()
35 do_div(ui, hs_clk_rate); in phy_mipi_dphy_get_default_config()
73 cfg->hs_clk_rate = hs_clk_rate; in phy_mipi_dphy_get_default_config()
91 ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
92 do_div(ui, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
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| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/phy/ |
| H A D | phy-core-mipi-dphy.c | 24 unsigned long long hs_clk_rate; in phy_mipi_dphy_get_default_config() local
30 hs_clk_rate = pixel_clock * bpp; in phy_mipi_dphy_get_default_config()
31 do_div(hs_clk_rate, lanes); in phy_mipi_dphy_get_default_config()
33 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); in phy_mipi_dphy_get_default_config()
34 do_div(ui, hs_clk_rate); in phy_mipi_dphy_get_default_config()
72 cfg->hs_clk_rate = hs_clk_rate; in phy_mipi_dphy_get_default_config()
89 ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
90 do_div(ui, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
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| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/phy/ |
| H A D | phy-core-mipi-dphy.c | 24 unsigned long long hs_clk_rate; in phy_mipi_dphy_get_default_config() local
30 hs_clk_rate = pixel_clock * bpp; in phy_mipi_dphy_get_default_config()
31 do_div(hs_clk_rate, lanes); in phy_mipi_dphy_get_default_config()
33 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); in phy_mipi_dphy_get_default_config()
34 do_div(ui, hs_clk_rate); in phy_mipi_dphy_get_default_config()
72 cfg->hs_clk_rate = hs_clk_rate; in phy_mipi_dphy_get_default_config()
89 ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
90 do_div(ui, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
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| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/phy/ |
| H A D | phy-core-mipi-dphy.c | 24 unsigned long long hs_clk_rate; in phy_mipi_dphy_get_default_config() local
30 hs_clk_rate = pixel_clock * bpp; in phy_mipi_dphy_get_default_config()
31 do_div(hs_clk_rate, lanes); in phy_mipi_dphy_get_default_config()
33 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); in phy_mipi_dphy_get_default_config()
34 do_div(ui, hs_clk_rate); in phy_mipi_dphy_get_default_config()
72 cfg->hs_clk_rate = hs_clk_rate; in phy_mipi_dphy_get_default_config()
89 ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
90 do_div(ui, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
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| /dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/phy/ |
| H A D | phy-core-mipi-dphy.c | 24 unsigned long long hs_clk_rate; in phy_mipi_dphy_get_default_config() local
30 hs_clk_rate = pixel_clock * bpp; in phy_mipi_dphy_get_default_config()
31 do_div(hs_clk_rate, lanes); in phy_mipi_dphy_get_default_config()
33 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); in phy_mipi_dphy_get_default_config()
34 do_div(ui, hs_clk_rate); in phy_mipi_dphy_get_default_config()
72 cfg->hs_clk_rate = hs_clk_rate; in phy_mipi_dphy_get_default_config()
89 ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
90 do_div(ui, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
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| /dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/phy/ |
| H A D | phy-core-mipi-dphy.c | 24 unsigned long long hs_clk_rate; in phy_mipi_dphy_get_default_config() local
30 hs_clk_rate = pixel_clock * bpp; in phy_mipi_dphy_get_default_config()
31 do_div(hs_clk_rate, lanes); in phy_mipi_dphy_get_default_config()
33 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); in phy_mipi_dphy_get_default_config()
34 do_div(ui, hs_clk_rate); in phy_mipi_dphy_get_default_config()
72 cfg->hs_clk_rate = hs_clk_rate; in phy_mipi_dphy_get_default_config()
89 ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
90 do_div(ui, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
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| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/phy/ |
| H A D | phy-core-mipi-dphy.c | 24 unsigned long long hs_clk_rate; in phy_mipi_dphy_get_default_config() local
30 hs_clk_rate = pixel_clock * bpp; in phy_mipi_dphy_get_default_config()
31 do_div(hs_clk_rate, lanes); in phy_mipi_dphy_get_default_config()
33 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); in phy_mipi_dphy_get_default_config()
34 do_div(ui, hs_clk_rate); in phy_mipi_dphy_get_default_config()
72 cfg->hs_clk_rate = hs_clk_rate; in phy_mipi_dphy_get_default_config()
89 ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
90 do_div(ui, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
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| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/phy/ |
| H A D | phy-core-mipi-dphy.c | 24 unsigned long long hs_clk_rate; in phy_mipi_dphy_get_default_config() local
30 hs_clk_rate = pixel_clock * bpp; in phy_mipi_dphy_get_default_config()
31 do_div(hs_clk_rate, lanes); in phy_mipi_dphy_get_default_config()
33 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); in phy_mipi_dphy_get_default_config()
34 do_div(ui, hs_clk_rate); in phy_mipi_dphy_get_default_config()
72 cfg->hs_clk_rate = hs_clk_rate; in phy_mipi_dphy_get_default_config()
89 ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
90 do_div(ui, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
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| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/drivers/phy/ |
| H A D | phy-core-mipi-dphy.c | 24 unsigned long long hs_clk_rate; in phy_mipi_dphy_get_default_config() local
30 hs_clk_rate = pixel_clock * bpp; in phy_mipi_dphy_get_default_config()
31 do_div(hs_clk_rate, lanes); in phy_mipi_dphy_get_default_config()
33 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); in phy_mipi_dphy_get_default_config()
34 do_div(ui, hs_clk_rate); in phy_mipi_dphy_get_default_config()
72 cfg->hs_clk_rate = hs_clk_rate; in phy_mipi_dphy_get_default_config()
89 ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
90 do_div(ui, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
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| /dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/drivers/phy/ |
| H A D | phy-core-mipi-dphy.c | 24 unsigned long long hs_clk_rate; in phy_mipi_dphy_get_default_config() local
30 hs_clk_rate = pixel_clock * bpp; in phy_mipi_dphy_get_default_config()
31 do_div(hs_clk_rate, lanes); in phy_mipi_dphy_get_default_config()
33 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); in phy_mipi_dphy_get_default_config()
34 do_div(ui, hs_clk_rate); in phy_mipi_dphy_get_default_config()
72 cfg->hs_clk_rate = hs_clk_rate; in phy_mipi_dphy_get_default_config()
89 ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
90 do_div(ui, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
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| /dports/sysutils/u-boot-pine64/u-boot-2021.07/drivers/phy/ |
| H A D | phy-core-mipi-dphy.c | 24 unsigned long long hs_clk_rate; in phy_mipi_dphy_get_default_config() local
30 hs_clk_rate = pixel_clock * bpp; in phy_mipi_dphy_get_default_config()
31 do_div(hs_clk_rate, lanes); in phy_mipi_dphy_get_default_config()
33 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); in phy_mipi_dphy_get_default_config()
34 do_div(ui, hs_clk_rate); in phy_mipi_dphy_get_default_config()
72 cfg->hs_clk_rate = hs_clk_rate; in phy_mipi_dphy_get_default_config()
89 ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
90 do_div(ui, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
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| /dports/sysutils/u-boot-pine-h64/u-boot-2021.07/drivers/phy/ |
| H A D | phy-core-mipi-dphy.c | 24 unsigned long long hs_clk_rate; in phy_mipi_dphy_get_default_config() local
30 hs_clk_rate = pixel_clock * bpp; in phy_mipi_dphy_get_default_config()
31 do_div(hs_clk_rate, lanes); in phy_mipi_dphy_get_default_config()
33 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); in phy_mipi_dphy_get_default_config()
34 do_div(ui, hs_clk_rate); in phy_mipi_dphy_get_default_config()
72 cfg->hs_clk_rate = hs_clk_rate; in phy_mipi_dphy_get_default_config()
89 ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
90 do_div(ui, cfg->hs_clk_rate); in phy_mipi_dphy_config_validate()
|