/dports/devel/directfb/DirectFB-1.4.17/gfxdrivers/cle266/ |
H A D | unichrome.c | 170 volatile u8* hwregs = ucdrv->hwregs; in uc_init_2d_engine() local 174 VIA_OUT(hwregs, 0x04, 0x0); in uc_init_2d_engine() 175 VIA_OUT(hwregs, 0x08, 0x0); in uc_init_2d_engine() 176 VIA_OUT(hwregs, 0x0c, 0x0); in uc_init_2d_engine() 177 VIA_OUT(hwregs, 0x10, 0x0); in uc_init_2d_engine() 178 VIA_OUT(hwregs, 0x14, 0x0); in uc_init_2d_engine() 179 VIA_OUT(hwregs, 0x18, 0x0); in uc_init_2d_engine() 180 VIA_OUT(hwregs, 0x1c, 0x0); in uc_init_2d_engine() 336 VGA_OUT8(ucdrv->hwregs, 0x3c5, VGA_IN8(ucdrv->hwregs, 0x3c5) & 0xbf); in uc_after_set_var() 338 VGA_OUT8(ucdrv->hwregs, 0x3c5, VGA_IN8(ucdrv->hwregs, 0x3c5) | 0x4); in uc_after_set_var() [all …]
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H A D | mmio.h | 18 #define VIA_OUT(hwregs, reg, val) *(volatile u32 *)((hwregs) + (reg)) = (val) argument 19 #define VIA_IN(hwregs, reg) *(volatile u32 *)((hwregs) + (reg)) argument 20 #define VGA_OUT8(hwregs, reg, val) *(volatile u8 *)((hwregs) + (reg) + 0x8000) = (val) argument 21 #define VGA_IN8(hwregs, reg) *(volatile u8 *)((hwregs) + (reg) + 0x8000) argument 28 #define VIA_OUT(hwregs, reg, val) *(volatile u32 *)((hwregs) + (reg)) = (val) argument 29 #define VIA_IN(hwregs, reg) *(volatile u32 *)((hwregs) + (reg)) argument 30 #define VGA_OUT8(hwregs, reg, val) *(volatile u8 *)((hwregs) + (reg) + 0x8000) = (val) argument 31 #define VGA_IN8(hwregs, reg) *(volatile u8 *)((hwregs) + (reg) + 0x8000) argument 38 #define VIDEO_OUT(hwregs, reg, val) VIA_OUT((hwregs)+0x200, reg, val) argument 39 #define VIDEO_IN(hwregs, reg) VIA_IN((hwregs)+0x200, reg) argument
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/dports/emulators/tilem/tilem-2.0/emu/x4/ |
H A D | x4_io.c | 42 i = (calc->hwregs[PORT2F] & 3); in set_lcd_wait_timer() 53 calc->hwregs[LCD_WAIT] = 1; in set_lcd_wait_timer() 80 return(calc->hwregs[PORT3]); in x4_z80_in() 107 return(calc->hwregs[PORT6]); in x4_z80_in() 110 return(calc->hwregs[PORT7]); in x4_z80_in() 113 return(calc->hwregs[PORT8]); in x4_z80_in() 189 return(calc->hwregs[PORT22]); in x4_z80_in() 192 return(calc->hwregs[PORT23]); in x4_z80_in() 195 return(calc->hwregs[PORT25]); in x4_z80_in() 349 byte lcdport = calc->hwregs[PORT29 + (calc->hwregs[PORT20] & 3)]; in setup_clockdelays() [all …]
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H A D | x4_init.c | 33 calc->hwregs[PORT3] = 0x0B; in x4_reset() 34 calc->hwregs[PORT4] = 0x07; in x4_reset() 35 calc->hwregs[PORT6] = 0x3F; in x4_reset() 36 calc->hwregs[PORT7] = 0x3F; in x4_reset() 45 calc->hwregs[PORT8] = 0x80; in x4_reset() 47 calc->hwregs[PORT20] = 0; in x4_reset() 48 calc->hwregs[PORT21] = 0; in x4_reset() 49 calc->hwregs[PORT22] = 0x08; in x4_reset() 50 calc->hwregs[PORT23] = 0x29; in x4_reset() 53 calc->hwregs[PORT27] = 0; in x4_reset() [all …]
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H A D | x4_memory.c | 39 if (A > (0xFFFF - 64 * calc->hwregs[PORT27])) in x4_z80_wrmem() 60 int state = calc->hwregs[PROTECTSTATE]; in readbyte() 70 calc->hwregs[PROTECTSTATE] = 0; in readbyte() 72 calc->hwregs[PROTECTSTATE] = 7; in readbyte() 74 calc->hwregs[PROTECTSTATE] = state + 1; in readbyte() 76 calc->hwregs[PROTECTSTATE] = 0; in readbyte() 90 if (A > (0xFFFF - 64 * calc->hwregs[PORT27])) in x4_z80_rdmem() 121 if (A > (0xFFFF - 64 * calc->hwregs[PORT27])) in x4_z80_rdmem_m1() 146 m = pa & calc->hwregs[NO_EXEC_RAM_MASK]; in x4_z80_rdmem_m1() 169 if (A > (0xFFFF - 64 * calc->hwregs[PORT27])) in x4_mem_ltop() [all …]
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/dports/emulators/tilem/tilem-2.0/emu/xz/ |
H A D | xz_io.c | 42 i = (calc->hwregs[PORT2F] & 3); in set_lcd_wait_timer() 53 calc->hwregs[LCD_WAIT] = 1; in set_lcd_wait_timer() 80 return(calc->hwregs[PORT3]); in xz_z80_in() 107 return(calc->hwregs[PORT6]); in xz_z80_in() 110 return(calc->hwregs[PORT7]); in xz_z80_in() 113 return(calc->hwregs[PORT8]); in xz_z80_in() 189 return(calc->hwregs[PORT22]); in xz_z80_in() 192 return(calc->hwregs[PORT23]); in xz_z80_in() 195 return(calc->hwregs[PORT25]); in xz_z80_in() 349 byte lcdport = calc->hwregs[PORT29 + (calc->hwregs[PORT20] & 3)]; in setup_clockdelays() [all …]
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H A D | xz_init.c | 33 calc->hwregs[PORT3] = 0x0B; in xz_reset() 34 calc->hwregs[PORT4] = 0x07; in xz_reset() 35 calc->hwregs[PORT6] = 0x7F; in xz_reset() 36 calc->hwregs[PORT7] = 0x7F; in xz_reset() 45 calc->hwregs[PORT8] = 0x80; in xz_reset() 47 calc->hwregs[PORT20] = 0; in xz_reset() 48 calc->hwregs[PORT21] = 1; in xz_reset() 49 calc->hwregs[PORT22] = 0x08; in xz_reset() 50 calc->hwregs[PORT23] = 0x69; in xz_reset() 53 calc->hwregs[PORT27] = 0; in xz_reset() [all …]
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H A D | xz_memory.c | 39 if (A > (0xFFFF - 64 * calc->hwregs[PORT27])) in xz_z80_wrmem() 60 int state = calc->hwregs[PROTECTSTATE]; in readbyte() 70 calc->hwregs[PROTECTSTATE] = 0; in readbyte() 72 calc->hwregs[PROTECTSTATE] = 7; in readbyte() 74 calc->hwregs[PROTECTSTATE] = state + 1; in readbyte() 76 calc->hwregs[PROTECTSTATE] = 0; in readbyte() 90 if (A > (0xFFFF - 64 * calc->hwregs[PORT27])) in xz_z80_rdmem() 121 if (A > (0xFFFF - 64 * calc->hwregs[PORT27])) in xz_z80_rdmem_m1() 146 m = pa & calc->hwregs[NO_EXEC_RAM_MASK]; in xz_z80_rdmem_m1() 169 if (A > (0xFFFF - 64 * calc->hwregs[PORT27])) in xz_mem_ltop() [all …]
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/dports/devel/directfb/DirectFB-1.4.17/gfxdrivers/unichrome/ |
H A D | unichrome.c | 205 volatile u8* hwregs = ucdrv->hwregs; in uc_init_2d_engine() local 211 VIA_OUT(hwregs, i, 0x0); in uc_init_2d_engine() 215 VIA_OUT(hwregs, 0x43c, 0x00100000); in uc_init_2d_engine() 216 VIA_OUT(hwregs, 0x440, 0x00000000); in uc_init_2d_engine() 217 VIA_OUT(hwregs, 0x440, 0x00333004); in uc_init_2d_engine() 337 VIA_OUT(hwregs, 0x43C,0x00fe0000); in uc_init_3d_engine() 338 VIA_OUT(hwregs, 0x440,0x08000001); in uc_init_3d_engine() 358 VGA_OUT8(ucdrv->hwregs, 0x3c5, VGA_IN8(ucdrv->hwregs, 0x3c5) & 0xbf); in uc_after_set_var() 360 VGA_OUT8(ucdrv->hwregs, 0x3c5, VGA_IN8(ucdrv->hwregs, 0x3c5) | 0x4); in uc_after_set_var() 362 …VIA_OUT(ucdrv->hwregs, VIA_REG_CURSOR_MODE, VIA_IN(ucdrv->hwregs, VIA_REG_CURSOR_MODE) & 0xFFFFFFF… in uc_after_set_var() [all …]
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H A D | mmio.h | 18 #define VIA_OUT(hwregs, reg, val) *(volatile u32 *)((hwregs) + (reg)) = (val) argument 19 #define VIA_IN(hwregs, reg) *(volatile u32 *)((hwregs) + (reg)) argument 20 #define VGA_OUT8(hwregs, reg, val) *(volatile u8 *)((hwregs) + (reg) + 0x8000) = (val) argument 21 #define VGA_IN8(hwregs, reg) *(volatile u8 *)((hwregs) + (reg) + 0x8000) argument 28 #define VIA_OUT(hwregs, reg, val) *(volatile u32 *)((hwregs) + (reg)) = (val) argument 29 #define VIA_IN(hwregs, reg) *(volatile u32 *)((hwregs) + (reg)) argument 30 #define VGA_OUT8(hwregs, reg, val) *(volatile u8 *)((hwregs) + (reg) + 0x8000) = (val) argument 31 #define VGA_IN8(hwregs, reg) *(volatile u8 *)((hwregs) + (reg) + 0x8000) argument 38 #define VIDEO_OUT(hwregs, reg, val) VIA_OUT((hwregs)+0x200, reg, val) argument 39 #define VIDEO_IN(hwregs, reg) VIA_IN((hwregs)+0x200, reg) argument
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H A D | uc_spic.c | 30 uc_spic_set_palette( volatile u8* hwregs, CorePalette *palette ) in uc_spic_set_palette() argument 37 VIDEO_OUT(hwregs, RAM_TABLE_CONTROL, in uc_spic_set_palette() 46 static void uc_spic_enable( volatile u8 *hwregs, bool enable ) in uc_spic_enable() argument 48 VIDEO_OUT(hwregs, SUBP_CONTROL_STRIDE, in uc_spic_enable() 57 VIDEO_OUT(hwregs, SUBP_STARTADDR, in uc_spic_set_buffer() 59 VIDEO_OUT(hwregs, SUBP_CONTROL_STRIDE, in uc_spic_set_buffer() 150 uc_spic_set_palette(ucdrv->hwregs, palette); in uc_spic_set_region() 151 uc_spic_set_buffer(ucdrv->hwregs, lock); in uc_spic_set_region() 152 uc_spic_enable(ucdrv->hwregs, (config->opacity > 0)); in uc_spic_set_region() 165 uc_spic_enable(ucdrv->hwregs, false); in uc_spic_remove() [all …]
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/dports/emulators/tilem/tilem-2.0/emu/xn/ |
H A D | xn_io.c | 42 i = (calc->hwregs[PORT2F] & 3); in set_lcd_wait_timer() 53 calc->hwregs[LCD_WAIT] = 1; in set_lcd_wait_timer() 83 return(calc->hwregs[PORT3]); in xn_z80_in() 110 return(calc->hwregs[PORT6]); in xn_z80_in() 113 return(calc->hwregs[PORT7]); in xn_z80_in() 116 return(calc->hwregs[PORT8]); in xn_z80_in() 192 return(calc->hwregs[PORT22]); in xn_z80_in() 195 return(calc->hwregs[PORT23]); in xn_z80_in() 198 return(calc->hwregs[PORT25]); in xn_z80_in() 352 byte lcdport = calc->hwregs[PORT29 + (calc->hwregs[PORT20] & 3)]; in setup_clockdelays() [all …]
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H A D | xn_init.c | 33 calc->hwregs[PORT3] = 0x0B; in xn_reset() 34 calc->hwregs[PORT4] = 0x07; in xn_reset() 35 calc->hwregs[PORT6] = 0x7F; in xn_reset() 36 calc->hwregs[PORT7] = 0x7F; in xn_reset() 45 calc->hwregs[PORT8] = 0x80; in xn_reset() 47 calc->hwregs[PORT20] = 0; in xn_reset() 48 calc->hwregs[PORT21] = 0; in xn_reset() 49 calc->hwregs[PORT22] = 0x08; in xn_reset() 50 calc->hwregs[PORT23] = 0x69; in xn_reset() 53 calc->hwregs[PORT27] = 0; in xn_reset() [all …]
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H A D | xn_memory.c | 39 if (A > (0xFFFF - 64 * calc->hwregs[PORT27])) in xn_z80_wrmem() 63 int state = calc->hwregs[PROTECTSTATE]; in readbyte() 70 calc->hwregs[PROTECTSTATE] = 0; in readbyte() 72 calc->hwregs[PROTECTSTATE] = 7; in readbyte() 74 calc->hwregs[PROTECTSTATE] = state + 1; in readbyte() 76 calc->hwregs[PROTECTSTATE] = 0; in readbyte() 90 if (A > (0xFFFF - 64 * calc->hwregs[PORT27])) in xn_z80_rdmem() 121 if (A > (0xFFFF - 64 * calc->hwregs[PORT27])) in xn_z80_rdmem_m1() 133 if (TILEM_UNLIKELY(page >= calc->hwregs[PORT22] in xn_z80_rdmem_m1() 134 && page <= calc->hwregs[PORT23])) { in xn_z80_rdmem_m1() [all …]
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/dports/emulators/tilem/tilem-2.0/emu/xs/ |
H A D | xs_io.c | 41 i = (calc->hwregs[PORT2F] & 3); in set_lcd_wait_timer() 52 calc->hwregs[LCD_WAIT] = 1; in set_lcd_wait_timer() 78 return(calc->hwregs[PORT3]); in xs_z80_in() 105 return(calc->hwregs[PORT6]); in xs_z80_in() 108 return(calc->hwregs[PORT7]); in xs_z80_in() 111 return(calc->hwregs[PORT8]); in xs_z80_in() 187 return(calc->hwregs[PORT22]); in xs_z80_in() 190 return(calc->hwregs[PORT23]); in xs_z80_in() 193 return(calc->hwregs[PORT25]); in xs_z80_in() 300 byte lcdport = calc->hwregs[PORT29 + (calc->hwregs[PORT20] & 3)]; in setup_clockdelays() [all …]
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H A D | xs_init.c | 35 calc->hwregs[PORT3] = 0x0B; in xs_reset() 36 calc->hwregs[PORT4] = 0x77; in xs_reset() 37 calc->hwregs[PORT6] = 0x7F; in xs_reset() 38 calc->hwregs[PORT7] = 0x7F; in xs_reset() 47 calc->hwregs[PORT8] = 0x80; in xs_reset() 49 calc->hwregs[PORT20] = 0; in xs_reset() 50 calc->hwregs[PORT21] = 1; in xs_reset() 51 calc->hwregs[PORT22] = 0x08; in xs_reset() 52 calc->hwregs[PORT23] = 0x69; in xs_reset() 55 calc->hwregs[PORT27] = 0; in xs_reset() [all …]
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H A D | xs_memory.c | 42 if (A > (0xFFFF - 64 * calc->hwregs[PORT27])) in xs_z80_wrmem() 63 int state = calc->hwregs[PROTECTSTATE]; in readbyte() 72 calc->hwregs[PROTECTSTATE] = 0; in readbyte() 74 calc->hwregs[PROTECTSTATE] = 7; in readbyte() 76 calc->hwregs[PROTECTSTATE] = state + 1; in readbyte() 78 calc->hwregs[PROTECTSTATE] = 0; in readbyte() 92 if (A > (0xFFFF - 64 * calc->hwregs[PORT27])) in xs_z80_rdmem() 123 if (A > (0xFFFF - 64 * calc->hwregs[PORT27])) in xs_z80_rdmem_m1() 152 m = pa & calc->hwregs[NO_EXEC_RAM_MASK]; in xs_z80_rdmem_m1() 175 if (A > (0xFFFF - 64 * calc->hwregs[PORT27])) in xs_mem_ltop() [all …]
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/dports/emulators/tilem/tilem-2.0/emu/x1/ |
H A D | x1_io.c | 43 return(calc->hwregs[PORT2]); in x1_z80_in() 56 return(calc->hwregs[PORT5]); in x1_z80_in() 59 return(calc->hwregs[PORT6]); in x1_z80_in() 79 if (calc->hwregs[PORT5] & 0x40) in setup_mapping() 127 calc->hwregs[HW_VERSION] = 1; in x1_z80_out() 132 calc->hwregs[HW_VERSION] = 2; in x1_z80_out() 151 calc->hwregs[PORT2] = value; in x1_z80_out() 170 calc->hwregs[PORT3] = value; in x1_z80_out() 175 calc->hwregs[PORT4] = value; in x1_z80_out() 200 calc->hwregs[PORT5] = value; in x1_z80_out() [all …]
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/dports/emulators/tilem/tilem-2.0/emu/x2/ |
H A D | x2_io.c | 58 return(calc->hwregs[PORT2]); in x2_z80_in() 96 if (calc->hwregs[PORT2] & 0x40) { in setup_mapping() 103 if (calc->hwregs[PORT2] & 0x80) { in setup_mapping() 110 if (calc->hwregs[PORT4] & 1) { in setup_mapping() 126 calc->hwregs[PORT0] = value; in x2_z80_out() 148 calc->hwregs[PORT2] = value; in x2_z80_out() 166 calc->hwregs[PORT3] = value; in x2_z80_out() 170 calc->hwregs[PORT4] = value; in x2_z80_out() 175 calc->hwregs[HW_VERSION] = 1; in x2_z80_out() 177 calc->hwregs[HW_VERSION] = 2; in x2_z80_out() [all …]
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/dports/emulators/tilem/tilem-2.0/emu/xp/ |
H A D | xp_io.c | 65 return(calc->hwregs[PORT3]); in xp_z80_in() 88 return(calc->hwregs[PORT6]); in xp_z80_in() 92 return(calc->hwregs[PORT7]); in xp_z80_in() 114 if (calc->hwregs[PORT6] & 0x40) in setup_mapping() 119 if (calc->hwregs[PORT7] & 0x40) in setup_mapping() 124 if (calc->hwregs[PORT4] & 1) { in setup_mapping() 185 calc->hwregs[PORT3] = value; in xp_z80_out() 190 calc->hwregs[PORT4] = value; in xp_z80_out() 245 switch(calc->hwregs[PORT5]) { in xp_z80_out() 274 if (calc->hwregs[PORT3] & 0x02) in xp_z80_ptimer() [all …]
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H A D | xp_init.c | 33 calc->hwregs[PORT3] = 0x0B; in xp_reset() 34 calc->hwregs[PORT4] = 0x77; in xp_reset() 35 calc->hwregs[PORT6] = 0x1F; in xp_reset() 36 calc->hwregs[PORT7] = 0x1F; in xp_reset() 45 calc->hwregs[PORT5] = 0; in xp_reset() 46 calc->hwregs[NOEXEC0] = 0; in xp_reset() 47 calc->hwregs[NOEXEC1] = 0; in xp_reset() 48 calc->hwregs[NOEXEC2] = 0; in xp_reset() 49 calc->hwregs[NOEXEC3] = 0; in xp_reset() 50 calc->hwregs[NOEXEC4] = 0; in xp_reset() [all …]
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/dports/emulators/tilem/tilem-2.0/emu/x3/ |
H A D | x3_io.c | 56 return(calc->hwregs[PORT2]); in x3_z80_in() 106 if (calc->hwregs[PORT2] & 0x40) { in setup_mapping() 110 pageA = (calc->hwregs[ROM_BANK] | (calc->hwregs[PORT2] & 7)); in setup_mapping() 113 if (calc->hwregs[PORT2] & 0x80) { in setup_mapping() 117 pageB = (calc->hwregs[ROM_BANK] | ((calc->hwregs[PORT2] >> 3) & 7)); in setup_mapping() 120 if (calc->hwregs[PORT4] & 1) { in setup_mapping() 150 calc->hwregs[PORT2] = value; in x3_z80_out() 170 calc->hwregs[PORT3] = value; in x3_z80_out() 174 calc->hwregs[PORT4] = value; in x3_z80_out() 200 if (calc->hwregs[PORT3] & 0x02) in x3_z80_ptimer() [all …]
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/dports/emulators/tilem/tilem-2.0/emu/x7/ |
H A D | x7_io.c | 58 return(calc->hwregs[PORT3]); in x7_z80_in() 77 return(calc->hwregs[PORT6]); in x7_z80_in() 81 return(calc->hwregs[PORT7]); in x7_z80_in() 103 if (calc->hwregs[PORT6] & 0x40) in setup_mapping() 108 if (calc->hwregs[PORT7] & 0x40) in setup_mapping() 113 if (calc->hwregs[PORT4] & 1) { in setup_mapping() 169 calc->hwregs[PORT3] = value; in x7_z80_out() 174 calc->hwregs[PORT4] = value; in x7_z80_out() 186 calc->hwregs[PORT6] = value & 0x7f; in x7_z80_out() 237 if (calc->hwregs[PORT3] & 0x02) in x7_z80_ptimer() [all …]
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/dports/emulators/tilem/tilem-2.0/emu/x5/ |
H A D | x5_io.c | 53 return(calc->hwregs[PORT5]); in x5_z80_in() 56 return(calc->hwregs[PORT6]); in x5_z80_in() 73 if (calc->hwregs[PORT5] & 0x40) { in setup_mapping() 77 pageA = (calc->hwregs[PORT5] & 7); in setup_mapping() 80 if (calc->hwregs[PORT6] & 0x40) { in setup_mapping() 123 calc->hwregs[PORT3] = value; in x5_z80_out() 129 calc->hwregs[PORT4] = value; in x5_z80_out() 152 calc->hwregs[PORT5] = value; in x5_z80_out() 157 calc->hwregs[PORT6] = value; in x5_z80_out() 163 calc->hwregs[PORT7] = value; in x5_z80_out() [all …]
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/dports/emulators/tilem/tilem-2.0/emu/x6/ |
H A D | x6_io.c | 53 return(calc->hwregs[PORT5]); in x6_z80_in() 56 return(calc->hwregs[PORT6]); in x6_z80_in() 73 if (calc->hwregs[PORT5] & 0x40) { in setup_mapping() 77 pageA = (calc->hwregs[PORT5] & 0x0f); in setup_mapping() 80 if (calc->hwregs[PORT6] & 0x40) { in setup_mapping() 123 calc->hwregs[PORT3] = value; in x6_z80_out() 129 calc->hwregs[PORT4] = value; in x6_z80_out() 152 calc->hwregs[PORT5] = value; in x6_z80_out() 157 calc->hwregs[PORT6] = value; in x6_z80_out() 163 calc->hwregs[PORT7] = value; in x6_z80_out() [all …]
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