| /dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/clk/imx/ |
| H A D | clk-imx8mq.c | 297 hws = clk_hw_data->hws; in imx8mq_clocks_probe()
423 hws[IMX8MQ_CLK_A53_CG] = hws[IMX8MQ_CLK_A53_DIV]; in imx8mq_clocks_probe()
424 hws[IMX8MQ_CLK_A53_SRC] = hws[IMX8MQ_CLK_A53_DIV]; in imx8mq_clocks_probe()
431 hws[IMX8MQ_CLK_M4_SRC] = hws[IMX8MQ_CLK_M4_CORE]; in imx8mq_clocks_probe()
432 hws[IMX8MQ_CLK_M4_CG] = hws[IMX8MQ_CLK_M4_CORE]; in imx8mq_clocks_probe()
433 hws[IMX8MQ_CLK_M4_DIV] = hws[IMX8MQ_CLK_M4_CORE]; in imx8mq_clocks_probe()
434 hws[IMX8MQ_CLK_VPU_SRC] = hws[IMX8MQ_CLK_VPU_CORE]; in imx8mq_clocks_probe()
435 hws[IMX8MQ_CLK_VPU_CG] = hws[IMX8MQ_CLK_VPU_CORE]; in imx8mq_clocks_probe()
436 hws[IMX8MQ_CLK_VPU_DIV] = hws[IMX8MQ_CLK_VPU_CORE]; in imx8mq_clocks_probe()
437 hws[IMX8MQ_CLK_GPU_CORE_SRC] = hws[IMX8MQ_CLK_GPU_CORE]; in imx8mq_clocks_probe()
[all …]
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| H A D | clk-imx8mm.c | 312 hws = clk_hw_data->hws; in imx8mm_clocks_probe()
424 hws[IMX8MM_CLK_A53_CG] = hws[IMX8MM_CLK_A53_DIV]; in imx8mm_clocks_probe()
425 hws[IMX8MM_CLK_A53_SRC] = hws[IMX8MM_CLK_A53_DIV]; in imx8mm_clocks_probe()
433 hws[IMX8MM_CLK_M4_SRC] = hws[IMX8MM_CLK_M4_CORE]; in imx8mm_clocks_probe()
434 hws[IMX8MM_CLK_M4_CG] = hws[IMX8MM_CLK_M4_CORE]; in imx8mm_clocks_probe()
435 hws[IMX8MM_CLK_M4_DIV] = hws[IMX8MM_CLK_M4_CORE]; in imx8mm_clocks_probe()
436 hws[IMX8MM_CLK_VPU_SRC] = hws[IMX8MM_CLK_VPU_CORE]; in imx8mm_clocks_probe()
437 hws[IMX8MM_CLK_VPU_CG] = hws[IMX8MM_CLK_VPU_CORE]; in imx8mm_clocks_probe()
438 hws[IMX8MM_CLK_VPU_DIV] = hws[IMX8MM_CLK_VPU_CORE]; in imx8mm_clocks_probe()
440 hws[IMX8MM_CLK_GPU3D_CG] = hws[IMX8MM_CLK_GPU3D_CORE]; in imx8mm_clocks_probe()
[all …]
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| H A D | clk-imx7d.c | 377 static struct clk_hw **hws; variable
391 hws = clk_hw_data->hws; in imx7d_clocks_init()
862 hws[IMX7D_ARM_A7_ROOT_CLK]->clk, in imx7d_clocks_init()
871 clk_set_parent(hws[IMX7D_PLL_ARM_MAIN_BYPASS]->clk, hws[IMX7D_PLL_ARM_MAIN]->clk); in imx7d_clocks_init()
872 clk_set_parent(hws[IMX7D_PLL_DRAM_MAIN_BYPASS]->clk, hws[IMX7D_PLL_DRAM_MAIN]->clk); in imx7d_clocks_init()
873 clk_set_parent(hws[IMX7D_PLL_SYS_MAIN_BYPASS]->clk, hws[IMX7D_PLL_SYS_MAIN]->clk); in imx7d_clocks_init()
874 clk_set_parent(hws[IMX7D_PLL_ENET_MAIN_BYPASS]->clk, hws[IMX7D_PLL_ENET_MAIN]->clk); in imx7d_clocks_init()
875 clk_set_parent(hws[IMX7D_PLL_AUDIO_MAIN_BYPASS]->clk, hws[IMX7D_PLL_AUDIO_MAIN]->clk); in imx7d_clocks_init()
876 clk_set_parent(hws[IMX7D_PLL_VIDEO_MAIN_BYPASS]->clk, hws[IMX7D_PLL_VIDEO_MAIN]->clk); in imx7d_clocks_init()
878 clk_set_parent(hws[IMX7D_MIPI_CSI_ROOT_SRC]->clk, hws[IMX7D_PLL_SYS_PFD3_CLK]->clk); in imx7d_clocks_init()
[all …]
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| H A D | clk-imx6ul.c | 125 hws = clk_hw_data->hws; in imx6ul_clocks_init()
167 clk_set_parent(hws[IMX6UL_PLL1_BYPASS]->clk, hws[IMX6UL_CLK_PLL1]->clk); in imx6ul_clocks_init()
168 clk_set_parent(hws[IMX6UL_PLL2_BYPASS]->clk, hws[IMX6UL_CLK_PLL2]->clk); in imx6ul_clocks_init()
169 clk_set_parent(hws[IMX6UL_PLL3_BYPASS]->clk, hws[IMX6UL_CLK_PLL3]->clk); in imx6ul_clocks_init()
170 clk_set_parent(hws[IMX6UL_PLL4_BYPASS]->clk, hws[IMX6UL_CLK_PLL4]->clk); in imx6ul_clocks_init()
171 clk_set_parent(hws[IMX6UL_PLL5_BYPASS]->clk, hws[IMX6UL_CLK_PLL5]->clk); in imx6ul_clocks_init()
172 clk_set_parent(hws[IMX6UL_PLL6_BYPASS]->clk, hws[IMX6UL_CLK_PLL6]->clk); in imx6ul_clocks_init()
173 clk_set_parent(hws[IMX6UL_PLL7_BYPASS]->clk, hws[IMX6UL_CLK_PLL7]->clk); in imx6ul_clocks_init()
486 clk_set_parent(hws[IMX6UL_CLK_PERIPH]->clk, hws[IMX6UL_CLK_PERIPH_PRE]->clk); in imx6ul_clocks_init()
492 clk_set_parent(hws[IMX6UL_CLK_PERCLK_SEL]->clk, hws[IMX6UL_CLK_OSC]->clk); in imx6ul_clocks_init()
[all …]
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| H A D | clk-imx6sx.c | 85 static struct clk_hw **hws; variable
131 hws = clk_hw_data->hws; in imx6sx_clocks_init()
177 clk_set_parent(hws[IMX6SX_PLL1_BYPASS]->clk, hws[IMX6SX_CLK_PLL1]->clk); in imx6sx_clocks_init()
178 clk_set_parent(hws[IMX6SX_PLL2_BYPASS]->clk, hws[IMX6SX_CLK_PLL2]->clk); in imx6sx_clocks_init()
179 clk_set_parent(hws[IMX6SX_PLL3_BYPASS]->clk, hws[IMX6SX_CLK_PLL3]->clk); in imx6sx_clocks_init()
180 clk_set_parent(hws[IMX6SX_PLL4_BYPASS]->clk, hws[IMX6SX_CLK_PLL4]->clk); in imx6sx_clocks_init()
181 clk_set_parent(hws[IMX6SX_PLL5_BYPASS]->clk, hws[IMX6SX_CLK_PLL5]->clk); in imx6sx_clocks_init()
182 clk_set_parent(hws[IMX6SX_PLL6_BYPASS]->clk, hws[IMX6SX_CLK_PLL6]->clk); in imx6sx_clocks_init()
183 clk_set_parent(hws[IMX6SX_PLL7_BYPASS]->clk, hws[IMX6SX_CLK_PLL7]->clk); in imx6sx_clocks_init()
514 clk_set_parent(hws[IMX6SX_CLK_ENET_SEL]->clk, hws[IMX6SX_CLK_ENET_PODF]->clk); in imx6sx_clocks_init()
[all …]
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| H A D | clk-imx8mp.c | 402 static struct clk_hw **hws; variable
431 hws = clk_hw_data->hws; in imx8mp_clocks_probe()
433 hws[IMX8MP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mp_clocks_probe()
524 hws[IMX8MP_CLK_A53_SRC] = hws[IMX8MP_CLK_A53_DIV]; in imx8mp_clocks_probe()
525 hws[IMX8MP_CLK_A53_CG] = hws[IMX8MP_CLK_A53_DIV]; in imx8mp_clocks_probe()
532 hws[IMX8MP_CLK_AUDIO_AXI_SRC] = hws[IMX8MP_CLK_AUDIO_AXI]; in imx8mp_clocks_probe()
707 hws[IMX8MP_CLK_A53_CORE]->clk, in imx8mp_clocks_probe()
708 hws[IMX8MP_CLK_A53_CORE]->clk, in imx8mp_clocks_probe()
709 hws[IMX8MP_ARM_PLL_OUT]->clk, in imx8mp_clocks_probe()
710 hws[IMX8MP_CLK_A53_DIV]->clk); in imx8mp_clocks_probe()
[all …]
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| H A D | clk-imx8mn.c | 290 static struct clk_hw **hws; variable
305 hws = clk_hw_data->hws; in imx8mn_clocks_probe()
421 hws[IMX8MN_CLK_A53_SRC] = hws[IMX8MN_CLK_A53_DIV]; in imx8mn_clocks_probe()
422 hws[IMX8MN_CLK_A53_CG] = hws[IMX8MN_CLK_A53_DIV]; in imx8mn_clocks_probe()
427 hws[IMX8MN_CLK_GPU_CORE_SRC] = hws[IMX8MN_CLK_GPU_CORE]; in imx8mn_clocks_probe()
428 hws[IMX8MN_CLK_GPU_CORE_CG] = hws[IMX8MN_CLK_GPU_CORE]; in imx8mn_clocks_probe()
429 hws[IMX8MN_CLK_GPU_CORE_DIV] = hws[IMX8MN_CLK_GPU_CORE]; in imx8mn_clocks_probe()
430 hws[IMX8MN_CLK_GPU_SHADER_SRC] = hws[IMX8MN_CLK_GPU_SHADER]; in imx8mn_clocks_probe()
431 hws[IMX8MN_CLK_GPU_SHADER_CG] = hws[IMX8MN_CLK_GPU_SHADER]; in imx8mn_clocks_probe()
432 hws[IMX8MN_CLK_GPU_SHADER_DIV] = hws[IMX8MN_CLK_GPU_SHADER]; in imx8mn_clocks_probe()
[all …]
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| H A D | clk-imx6q.c | 92 static struct clk_hw **hws; variable
443 hws = clk_hw_data->hws; in imx6q_clocks_init()
494 clk_set_parent(hws[IMX6QDL_PLL1_BYPASS]->clk, hws[IMX6QDL_CLK_PLL1]->clk); in imx6q_clocks_init()
495 clk_set_parent(hws[IMX6QDL_PLL2_BYPASS]->clk, hws[IMX6QDL_CLK_PLL2]->clk); in imx6q_clocks_init()
496 clk_set_parent(hws[IMX6QDL_PLL3_BYPASS]->clk, hws[IMX6QDL_CLK_PLL3]->clk); in imx6q_clocks_init()
497 clk_set_parent(hws[IMX6QDL_PLL4_BYPASS]->clk, hws[IMX6QDL_CLK_PLL4]->clk); in imx6q_clocks_init()
498 clk_set_parent(hws[IMX6QDL_PLL5_BYPASS]->clk, hws[IMX6QDL_CLK_PLL5]->clk); in imx6q_clocks_init()
499 clk_set_parent(hws[IMX6QDL_PLL6_BYPASS]->clk, hws[IMX6QDL_CLK_PLL6]->clk); in imx6q_clocks_init()
500 clk_set_parent(hws[IMX6QDL_PLL7_BYPASS]->clk, hws[IMX6QDL_CLK_PLL7]->clk); in imx6q_clocks_init()
909 hws[IMX6QDL_CLK_GPT_3M] = hws[IMX6QDL_CLK_GPT_IPG_PER]; in imx6q_clocks_init()
[all …]
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| H A D | clk-imx6sl.c | 100 static struct clk_hw **hws; variable
194 hws = clk_hw_data->hws; in imx6sl_clocks_init()
234 clk_set_parent(hws[IMX6SL_PLL1_BYPASS]->clk, hws[IMX6SL_CLK_PLL1]->clk); in imx6sl_clocks_init()
235 clk_set_parent(hws[IMX6SL_PLL2_BYPASS]->clk, hws[IMX6SL_CLK_PLL2]->clk); in imx6sl_clocks_init()
236 clk_set_parent(hws[IMX6SL_PLL3_BYPASS]->clk, hws[IMX6SL_CLK_PLL3]->clk); in imx6sl_clocks_init()
237 clk_set_parent(hws[IMX6SL_PLL4_BYPASS]->clk, hws[IMX6SL_CLK_PLL4]->clk); in imx6sl_clocks_init()
238 clk_set_parent(hws[IMX6SL_PLL5_BYPASS]->clk, hws[IMX6SL_CLK_PLL5]->clk); in imx6sl_clocks_init()
239 clk_set_parent(hws[IMX6SL_PLL6_BYPASS]->clk, hws[IMX6SL_CLK_PLL6]->clk); in imx6sl_clocks_init()
240 clk_set_parent(hws[IMX6SL_PLL7_BYPASS]->clk, hws[IMX6SL_CLK_PLL7]->clk); in imx6sl_clocks_init()
418 imx_check_clk_hws(hws, IMX6SL_CLK_END); in imx6sl_clocks_init()
[all …]
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| /dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/clk/imx/ |
| H A D | clk-imx8mq.c | 297 hws = clk_hw_data->hws; in imx8mq_clocks_probe()
423 hws[IMX8MQ_CLK_A53_CG] = hws[IMX8MQ_CLK_A53_DIV]; in imx8mq_clocks_probe()
424 hws[IMX8MQ_CLK_A53_SRC] = hws[IMX8MQ_CLK_A53_DIV]; in imx8mq_clocks_probe()
431 hws[IMX8MQ_CLK_M4_SRC] = hws[IMX8MQ_CLK_M4_CORE]; in imx8mq_clocks_probe()
432 hws[IMX8MQ_CLK_M4_CG] = hws[IMX8MQ_CLK_M4_CORE]; in imx8mq_clocks_probe()
433 hws[IMX8MQ_CLK_M4_DIV] = hws[IMX8MQ_CLK_M4_CORE]; in imx8mq_clocks_probe()
434 hws[IMX8MQ_CLK_VPU_SRC] = hws[IMX8MQ_CLK_VPU_CORE]; in imx8mq_clocks_probe()
435 hws[IMX8MQ_CLK_VPU_CG] = hws[IMX8MQ_CLK_VPU_CORE]; in imx8mq_clocks_probe()
436 hws[IMX8MQ_CLK_VPU_DIV] = hws[IMX8MQ_CLK_VPU_CORE]; in imx8mq_clocks_probe()
437 hws[IMX8MQ_CLK_GPU_CORE_SRC] = hws[IMX8MQ_CLK_GPU_CORE]; in imx8mq_clocks_probe()
[all …]
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| H A D | clk-imx8mm.c | 312 hws = clk_hw_data->hws; in imx8mm_clocks_probe()
424 hws[IMX8MM_CLK_A53_CG] = hws[IMX8MM_CLK_A53_DIV]; in imx8mm_clocks_probe()
425 hws[IMX8MM_CLK_A53_SRC] = hws[IMX8MM_CLK_A53_DIV]; in imx8mm_clocks_probe()
433 hws[IMX8MM_CLK_M4_SRC] = hws[IMX8MM_CLK_M4_CORE]; in imx8mm_clocks_probe()
434 hws[IMX8MM_CLK_M4_CG] = hws[IMX8MM_CLK_M4_CORE]; in imx8mm_clocks_probe()
435 hws[IMX8MM_CLK_M4_DIV] = hws[IMX8MM_CLK_M4_CORE]; in imx8mm_clocks_probe()
436 hws[IMX8MM_CLK_VPU_SRC] = hws[IMX8MM_CLK_VPU_CORE]; in imx8mm_clocks_probe()
437 hws[IMX8MM_CLK_VPU_CG] = hws[IMX8MM_CLK_VPU_CORE]; in imx8mm_clocks_probe()
438 hws[IMX8MM_CLK_VPU_DIV] = hws[IMX8MM_CLK_VPU_CORE]; in imx8mm_clocks_probe()
440 hws[IMX8MM_CLK_GPU3D_CG] = hws[IMX8MM_CLK_GPU3D_CORE]; in imx8mm_clocks_probe()
[all …]
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| H A D | clk-imx7d.c | 377 static struct clk_hw **hws; variable
391 hws = clk_hw_data->hws; in imx7d_clocks_init()
862 hws[IMX7D_ARM_A7_ROOT_CLK]->clk, in imx7d_clocks_init()
871 clk_set_parent(hws[IMX7D_PLL_ARM_MAIN_BYPASS]->clk, hws[IMX7D_PLL_ARM_MAIN]->clk); in imx7d_clocks_init()
872 clk_set_parent(hws[IMX7D_PLL_DRAM_MAIN_BYPASS]->clk, hws[IMX7D_PLL_DRAM_MAIN]->clk); in imx7d_clocks_init()
873 clk_set_parent(hws[IMX7D_PLL_SYS_MAIN_BYPASS]->clk, hws[IMX7D_PLL_SYS_MAIN]->clk); in imx7d_clocks_init()
874 clk_set_parent(hws[IMX7D_PLL_ENET_MAIN_BYPASS]->clk, hws[IMX7D_PLL_ENET_MAIN]->clk); in imx7d_clocks_init()
875 clk_set_parent(hws[IMX7D_PLL_AUDIO_MAIN_BYPASS]->clk, hws[IMX7D_PLL_AUDIO_MAIN]->clk); in imx7d_clocks_init()
876 clk_set_parent(hws[IMX7D_PLL_VIDEO_MAIN_BYPASS]->clk, hws[IMX7D_PLL_VIDEO_MAIN]->clk); in imx7d_clocks_init()
878 clk_set_parent(hws[IMX7D_MIPI_CSI_ROOT_SRC]->clk, hws[IMX7D_PLL_SYS_PFD3_CLK]->clk); in imx7d_clocks_init()
[all …]
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| H A D | clk-imx6ul.c | 125 hws = clk_hw_data->hws; in imx6ul_clocks_init()
167 clk_set_parent(hws[IMX6UL_PLL1_BYPASS]->clk, hws[IMX6UL_CLK_PLL1]->clk); in imx6ul_clocks_init()
168 clk_set_parent(hws[IMX6UL_PLL2_BYPASS]->clk, hws[IMX6UL_CLK_PLL2]->clk); in imx6ul_clocks_init()
169 clk_set_parent(hws[IMX6UL_PLL3_BYPASS]->clk, hws[IMX6UL_CLK_PLL3]->clk); in imx6ul_clocks_init()
170 clk_set_parent(hws[IMX6UL_PLL4_BYPASS]->clk, hws[IMX6UL_CLK_PLL4]->clk); in imx6ul_clocks_init()
171 clk_set_parent(hws[IMX6UL_PLL5_BYPASS]->clk, hws[IMX6UL_CLK_PLL5]->clk); in imx6ul_clocks_init()
172 clk_set_parent(hws[IMX6UL_PLL6_BYPASS]->clk, hws[IMX6UL_CLK_PLL6]->clk); in imx6ul_clocks_init()
173 clk_set_parent(hws[IMX6UL_PLL7_BYPASS]->clk, hws[IMX6UL_CLK_PLL7]->clk); in imx6ul_clocks_init()
486 clk_set_parent(hws[IMX6UL_CLK_PERIPH]->clk, hws[IMX6UL_CLK_PERIPH_PRE]->clk); in imx6ul_clocks_init()
492 clk_set_parent(hws[IMX6UL_CLK_PERCLK_SEL]->clk, hws[IMX6UL_CLK_OSC]->clk); in imx6ul_clocks_init()
[all …]
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| H A D | clk-imx6sx.c | 85 static struct clk_hw **hws; variable
131 hws = clk_hw_data->hws; in imx6sx_clocks_init()
177 clk_set_parent(hws[IMX6SX_PLL1_BYPASS]->clk, hws[IMX6SX_CLK_PLL1]->clk); in imx6sx_clocks_init()
178 clk_set_parent(hws[IMX6SX_PLL2_BYPASS]->clk, hws[IMX6SX_CLK_PLL2]->clk); in imx6sx_clocks_init()
179 clk_set_parent(hws[IMX6SX_PLL3_BYPASS]->clk, hws[IMX6SX_CLK_PLL3]->clk); in imx6sx_clocks_init()
180 clk_set_parent(hws[IMX6SX_PLL4_BYPASS]->clk, hws[IMX6SX_CLK_PLL4]->clk); in imx6sx_clocks_init()
181 clk_set_parent(hws[IMX6SX_PLL5_BYPASS]->clk, hws[IMX6SX_CLK_PLL5]->clk); in imx6sx_clocks_init()
182 clk_set_parent(hws[IMX6SX_PLL6_BYPASS]->clk, hws[IMX6SX_CLK_PLL6]->clk); in imx6sx_clocks_init()
183 clk_set_parent(hws[IMX6SX_PLL7_BYPASS]->clk, hws[IMX6SX_CLK_PLL7]->clk); in imx6sx_clocks_init()
514 clk_set_parent(hws[IMX6SX_CLK_ENET_SEL]->clk, hws[IMX6SX_CLK_ENET_PODF]->clk); in imx6sx_clocks_init()
[all …]
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| H A D | clk-imx8mp.c | 402 static struct clk_hw **hws; variable
431 hws = clk_hw_data->hws; in imx8mp_clocks_probe()
433 hws[IMX8MP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mp_clocks_probe()
524 hws[IMX8MP_CLK_A53_SRC] = hws[IMX8MP_CLK_A53_DIV]; in imx8mp_clocks_probe()
525 hws[IMX8MP_CLK_A53_CG] = hws[IMX8MP_CLK_A53_DIV]; in imx8mp_clocks_probe()
532 hws[IMX8MP_CLK_AUDIO_AXI_SRC] = hws[IMX8MP_CLK_AUDIO_AXI]; in imx8mp_clocks_probe()
707 hws[IMX8MP_CLK_A53_CORE]->clk, in imx8mp_clocks_probe()
708 hws[IMX8MP_CLK_A53_CORE]->clk, in imx8mp_clocks_probe()
709 hws[IMX8MP_ARM_PLL_OUT]->clk, in imx8mp_clocks_probe()
710 hws[IMX8MP_CLK_A53_DIV]->clk); in imx8mp_clocks_probe()
[all …]
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| H A D | clk-imx8mn.c | 290 static struct clk_hw **hws; variable
305 hws = clk_hw_data->hws; in imx8mn_clocks_probe()
421 hws[IMX8MN_CLK_A53_SRC] = hws[IMX8MN_CLK_A53_DIV]; in imx8mn_clocks_probe()
422 hws[IMX8MN_CLK_A53_CG] = hws[IMX8MN_CLK_A53_DIV]; in imx8mn_clocks_probe()
427 hws[IMX8MN_CLK_GPU_CORE_SRC] = hws[IMX8MN_CLK_GPU_CORE]; in imx8mn_clocks_probe()
428 hws[IMX8MN_CLK_GPU_CORE_CG] = hws[IMX8MN_CLK_GPU_CORE]; in imx8mn_clocks_probe()
429 hws[IMX8MN_CLK_GPU_CORE_DIV] = hws[IMX8MN_CLK_GPU_CORE]; in imx8mn_clocks_probe()
430 hws[IMX8MN_CLK_GPU_SHADER_SRC] = hws[IMX8MN_CLK_GPU_SHADER]; in imx8mn_clocks_probe()
431 hws[IMX8MN_CLK_GPU_SHADER_CG] = hws[IMX8MN_CLK_GPU_SHADER]; in imx8mn_clocks_probe()
432 hws[IMX8MN_CLK_GPU_SHADER_DIV] = hws[IMX8MN_CLK_GPU_SHADER]; in imx8mn_clocks_probe()
[all …]
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| H A D | clk-imx6q.c | 92 static struct clk_hw **hws; variable
443 hws = clk_hw_data->hws; in imx6q_clocks_init()
494 clk_set_parent(hws[IMX6QDL_PLL1_BYPASS]->clk, hws[IMX6QDL_CLK_PLL1]->clk); in imx6q_clocks_init()
495 clk_set_parent(hws[IMX6QDL_PLL2_BYPASS]->clk, hws[IMX6QDL_CLK_PLL2]->clk); in imx6q_clocks_init()
496 clk_set_parent(hws[IMX6QDL_PLL3_BYPASS]->clk, hws[IMX6QDL_CLK_PLL3]->clk); in imx6q_clocks_init()
497 clk_set_parent(hws[IMX6QDL_PLL4_BYPASS]->clk, hws[IMX6QDL_CLK_PLL4]->clk); in imx6q_clocks_init()
498 clk_set_parent(hws[IMX6QDL_PLL5_BYPASS]->clk, hws[IMX6QDL_CLK_PLL5]->clk); in imx6q_clocks_init()
499 clk_set_parent(hws[IMX6QDL_PLL6_BYPASS]->clk, hws[IMX6QDL_CLK_PLL6]->clk); in imx6q_clocks_init()
500 clk_set_parent(hws[IMX6QDL_PLL7_BYPASS]->clk, hws[IMX6QDL_CLK_PLL7]->clk); in imx6q_clocks_init()
909 hws[IMX6QDL_CLK_GPT_3M] = hws[IMX6QDL_CLK_GPT_IPG_PER]; in imx6q_clocks_init()
[all …]
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| /dports/multimedia/libv4l/linux-5.13-rc2/drivers/clk/imx/ |
| H A D | clk-imx8mq.c | 297 hws = clk_hw_data->hws; in imx8mq_clocks_probe()
423 hws[IMX8MQ_CLK_A53_CG] = hws[IMX8MQ_CLK_A53_DIV]; in imx8mq_clocks_probe()
424 hws[IMX8MQ_CLK_A53_SRC] = hws[IMX8MQ_CLK_A53_DIV]; in imx8mq_clocks_probe()
431 hws[IMX8MQ_CLK_M4_SRC] = hws[IMX8MQ_CLK_M4_CORE]; in imx8mq_clocks_probe()
432 hws[IMX8MQ_CLK_M4_CG] = hws[IMX8MQ_CLK_M4_CORE]; in imx8mq_clocks_probe()
433 hws[IMX8MQ_CLK_M4_DIV] = hws[IMX8MQ_CLK_M4_CORE]; in imx8mq_clocks_probe()
434 hws[IMX8MQ_CLK_VPU_SRC] = hws[IMX8MQ_CLK_VPU_CORE]; in imx8mq_clocks_probe()
435 hws[IMX8MQ_CLK_VPU_CG] = hws[IMX8MQ_CLK_VPU_CORE]; in imx8mq_clocks_probe()
436 hws[IMX8MQ_CLK_VPU_DIV] = hws[IMX8MQ_CLK_VPU_CORE]; in imx8mq_clocks_probe()
437 hws[IMX8MQ_CLK_GPU_CORE_SRC] = hws[IMX8MQ_CLK_GPU_CORE]; in imx8mq_clocks_probe()
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| H A D | clk-imx8mm.c | 312 hws = clk_hw_data->hws; in imx8mm_clocks_probe()
424 hws[IMX8MM_CLK_A53_CG] = hws[IMX8MM_CLK_A53_DIV]; in imx8mm_clocks_probe()
425 hws[IMX8MM_CLK_A53_SRC] = hws[IMX8MM_CLK_A53_DIV]; in imx8mm_clocks_probe()
433 hws[IMX8MM_CLK_M4_SRC] = hws[IMX8MM_CLK_M4_CORE]; in imx8mm_clocks_probe()
434 hws[IMX8MM_CLK_M4_CG] = hws[IMX8MM_CLK_M4_CORE]; in imx8mm_clocks_probe()
435 hws[IMX8MM_CLK_M4_DIV] = hws[IMX8MM_CLK_M4_CORE]; in imx8mm_clocks_probe()
436 hws[IMX8MM_CLK_VPU_SRC] = hws[IMX8MM_CLK_VPU_CORE]; in imx8mm_clocks_probe()
437 hws[IMX8MM_CLK_VPU_CG] = hws[IMX8MM_CLK_VPU_CORE]; in imx8mm_clocks_probe()
438 hws[IMX8MM_CLK_VPU_DIV] = hws[IMX8MM_CLK_VPU_CORE]; in imx8mm_clocks_probe()
440 hws[IMX8MM_CLK_GPU3D_CG] = hws[IMX8MM_CLK_GPU3D_CORE]; in imx8mm_clocks_probe()
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| H A D | clk-imx7d.c | 377 static struct clk_hw **hws; variable
391 hws = clk_hw_data->hws; in imx7d_clocks_init()
862 hws[IMX7D_ARM_A7_ROOT_CLK]->clk, in imx7d_clocks_init()
871 clk_set_parent(hws[IMX7D_PLL_ARM_MAIN_BYPASS]->clk, hws[IMX7D_PLL_ARM_MAIN]->clk); in imx7d_clocks_init()
872 clk_set_parent(hws[IMX7D_PLL_DRAM_MAIN_BYPASS]->clk, hws[IMX7D_PLL_DRAM_MAIN]->clk); in imx7d_clocks_init()
873 clk_set_parent(hws[IMX7D_PLL_SYS_MAIN_BYPASS]->clk, hws[IMX7D_PLL_SYS_MAIN]->clk); in imx7d_clocks_init()
874 clk_set_parent(hws[IMX7D_PLL_ENET_MAIN_BYPASS]->clk, hws[IMX7D_PLL_ENET_MAIN]->clk); in imx7d_clocks_init()
875 clk_set_parent(hws[IMX7D_PLL_AUDIO_MAIN_BYPASS]->clk, hws[IMX7D_PLL_AUDIO_MAIN]->clk); in imx7d_clocks_init()
876 clk_set_parent(hws[IMX7D_PLL_VIDEO_MAIN_BYPASS]->clk, hws[IMX7D_PLL_VIDEO_MAIN]->clk); in imx7d_clocks_init()
878 clk_set_parent(hws[IMX7D_MIPI_CSI_ROOT_SRC]->clk, hws[IMX7D_PLL_SYS_PFD3_CLK]->clk); in imx7d_clocks_init()
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| H A D | clk-imx6ul.c | 125 hws = clk_hw_data->hws; in imx6ul_clocks_init()
167 clk_set_parent(hws[IMX6UL_PLL1_BYPASS]->clk, hws[IMX6UL_CLK_PLL1]->clk); in imx6ul_clocks_init()
168 clk_set_parent(hws[IMX6UL_PLL2_BYPASS]->clk, hws[IMX6UL_CLK_PLL2]->clk); in imx6ul_clocks_init()
169 clk_set_parent(hws[IMX6UL_PLL3_BYPASS]->clk, hws[IMX6UL_CLK_PLL3]->clk); in imx6ul_clocks_init()
170 clk_set_parent(hws[IMX6UL_PLL4_BYPASS]->clk, hws[IMX6UL_CLK_PLL4]->clk); in imx6ul_clocks_init()
171 clk_set_parent(hws[IMX6UL_PLL5_BYPASS]->clk, hws[IMX6UL_CLK_PLL5]->clk); in imx6ul_clocks_init()
172 clk_set_parent(hws[IMX6UL_PLL6_BYPASS]->clk, hws[IMX6UL_CLK_PLL6]->clk); in imx6ul_clocks_init()
173 clk_set_parent(hws[IMX6UL_PLL7_BYPASS]->clk, hws[IMX6UL_CLK_PLL7]->clk); in imx6ul_clocks_init()
486 clk_set_parent(hws[IMX6UL_CLK_PERIPH]->clk, hws[IMX6UL_CLK_PERIPH_PRE]->clk); in imx6ul_clocks_init()
492 clk_set_parent(hws[IMX6UL_CLK_PERCLK_SEL]->clk, hws[IMX6UL_CLK_OSC]->clk); in imx6ul_clocks_init()
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| H A D | clk-imx6sx.c | 85 static struct clk_hw **hws; variable
131 hws = clk_hw_data->hws; in imx6sx_clocks_init()
177 clk_set_parent(hws[IMX6SX_PLL1_BYPASS]->clk, hws[IMX6SX_CLK_PLL1]->clk); in imx6sx_clocks_init()
178 clk_set_parent(hws[IMX6SX_PLL2_BYPASS]->clk, hws[IMX6SX_CLK_PLL2]->clk); in imx6sx_clocks_init()
179 clk_set_parent(hws[IMX6SX_PLL3_BYPASS]->clk, hws[IMX6SX_CLK_PLL3]->clk); in imx6sx_clocks_init()
180 clk_set_parent(hws[IMX6SX_PLL4_BYPASS]->clk, hws[IMX6SX_CLK_PLL4]->clk); in imx6sx_clocks_init()
181 clk_set_parent(hws[IMX6SX_PLL5_BYPASS]->clk, hws[IMX6SX_CLK_PLL5]->clk); in imx6sx_clocks_init()
182 clk_set_parent(hws[IMX6SX_PLL6_BYPASS]->clk, hws[IMX6SX_CLK_PLL6]->clk); in imx6sx_clocks_init()
183 clk_set_parent(hws[IMX6SX_PLL7_BYPASS]->clk, hws[IMX6SX_CLK_PLL7]->clk); in imx6sx_clocks_init()
514 clk_set_parent(hws[IMX6SX_CLK_ENET_SEL]->clk, hws[IMX6SX_CLK_ENET_PODF]->clk); in imx6sx_clocks_init()
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| H A D | clk-imx8mp.c | 402 static struct clk_hw **hws; variable
431 hws = clk_hw_data->hws; in imx8mp_clocks_probe()
433 hws[IMX8MP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mp_clocks_probe()
524 hws[IMX8MP_CLK_A53_SRC] = hws[IMX8MP_CLK_A53_DIV]; in imx8mp_clocks_probe()
525 hws[IMX8MP_CLK_A53_CG] = hws[IMX8MP_CLK_A53_DIV]; in imx8mp_clocks_probe()
532 hws[IMX8MP_CLK_AUDIO_AXI_SRC] = hws[IMX8MP_CLK_AUDIO_AXI]; in imx8mp_clocks_probe()
707 hws[IMX8MP_CLK_A53_CORE]->clk, in imx8mp_clocks_probe()
708 hws[IMX8MP_CLK_A53_CORE]->clk, in imx8mp_clocks_probe()
709 hws[IMX8MP_ARM_PLL_OUT]->clk, in imx8mp_clocks_probe()
710 hws[IMX8MP_CLK_A53_DIV]->clk); in imx8mp_clocks_probe()
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| H A D | clk-imx8mn.c | 290 static struct clk_hw **hws; variable
305 hws = clk_hw_data->hws; in imx8mn_clocks_probe()
421 hws[IMX8MN_CLK_A53_SRC] = hws[IMX8MN_CLK_A53_DIV]; in imx8mn_clocks_probe()
422 hws[IMX8MN_CLK_A53_CG] = hws[IMX8MN_CLK_A53_DIV]; in imx8mn_clocks_probe()
427 hws[IMX8MN_CLK_GPU_CORE_SRC] = hws[IMX8MN_CLK_GPU_CORE]; in imx8mn_clocks_probe()
428 hws[IMX8MN_CLK_GPU_CORE_CG] = hws[IMX8MN_CLK_GPU_CORE]; in imx8mn_clocks_probe()
429 hws[IMX8MN_CLK_GPU_CORE_DIV] = hws[IMX8MN_CLK_GPU_CORE]; in imx8mn_clocks_probe()
430 hws[IMX8MN_CLK_GPU_SHADER_SRC] = hws[IMX8MN_CLK_GPU_SHADER]; in imx8mn_clocks_probe()
431 hws[IMX8MN_CLK_GPU_SHADER_CG] = hws[IMX8MN_CLK_GPU_SHADER]; in imx8mn_clocks_probe()
432 hws[IMX8MN_CLK_GPU_SHADER_DIV] = hws[IMX8MN_CLK_GPU_SHADER]; in imx8mn_clocks_probe()
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| H A D | clk-imx6q.c | 92 static struct clk_hw **hws; variable
443 hws = clk_hw_data->hws; in imx6q_clocks_init()
494 clk_set_parent(hws[IMX6QDL_PLL1_BYPASS]->clk, hws[IMX6QDL_CLK_PLL1]->clk); in imx6q_clocks_init()
495 clk_set_parent(hws[IMX6QDL_PLL2_BYPASS]->clk, hws[IMX6QDL_CLK_PLL2]->clk); in imx6q_clocks_init()
496 clk_set_parent(hws[IMX6QDL_PLL3_BYPASS]->clk, hws[IMX6QDL_CLK_PLL3]->clk); in imx6q_clocks_init()
497 clk_set_parent(hws[IMX6QDL_PLL4_BYPASS]->clk, hws[IMX6QDL_CLK_PLL4]->clk); in imx6q_clocks_init()
498 clk_set_parent(hws[IMX6QDL_PLL5_BYPASS]->clk, hws[IMX6QDL_CLK_PLL5]->clk); in imx6q_clocks_init()
499 clk_set_parent(hws[IMX6QDL_PLL6_BYPASS]->clk, hws[IMX6QDL_CLK_PLL6]->clk); in imx6q_clocks_init()
500 clk_set_parent(hws[IMX6QDL_PLL7_BYPASS]->clk, hws[IMX6QDL_CLK_PLL7]->clk); in imx6q_clocks_init()
909 hws[IMX6QDL_CLK_GPT_3M] = hws[IMX6QDL_CLK_GPT_IPG_PER]; in imx6q_clocks_init()
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