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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/X86/
H A Dsmul-with-overflow.ll71 declare { i63, i1 } @llvm.smul.with.overflow.i63(i63, i63) nounwind readnone
75 %res = call { i63, i1 } @llvm.smul.with.overflow.i63(i63 4, i63 4611686018427387903)
76 %sum = extractvalue { i63, i1 } %res, 0
77 %overflow = extractvalue { i63, i1 } %res, 1
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/X86/
H A Dsmul-with-overflow.ll71 declare { i63, i1 } @llvm.smul.with.overflow.i63(i63, i63) nounwind readnone
75 %res = call { i63, i1 } @llvm.smul.with.overflow.i63(i63 4, i63 4611686018427387903)
76 %sum = extractvalue { i63, i1 } %res, 0
77 %overflow = extractvalue { i63, i1 } %res, 1
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/X86/
H A Dsmul-with-overflow.ll71 declare { i63, i1 } @llvm.smul.with.overflow.i63(i63, i63) nounwind readnone
75 %res = call { i63, i1 } @llvm.smul.with.overflow.i63(i63 4, i63 4611686018427387903)
76 %sum = extractvalue { i63, i1 } %res, 0
77 %overflow = extractvalue { i63, i1 } %res, 1
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/X86/
H A Dsmul-with-overflow.ll71 declare { i63, i1 } @llvm.smul.with.overflow.i63(i63, i63) nounwind readnone
75 %res = call { i63, i1 } @llvm.smul.with.overflow.i63(i63 4, i63 4611686018427387903)
76 %sum = extractvalue { i63, i1 } %res, 0
77 %overflow = extractvalue { i63, i1 } %res, 1
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/X86/
H A Dsmul-with-overflow.ll71 declare { i63, i1 } @llvm.smul.with.overflow.i63(i63, i63) nounwind readnone
75 %res = call { i63, i1 } @llvm.smul.with.overflow.i63(i63 4, i63 4611686018427387903)
76 %sum = extractvalue { i63, i1 } %res, 0
77 %overflow = extractvalue { i63, i1 } %res, 1
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/X86/
H A Dsmul-with-overflow.ll71 declare { i63, i1 } @llvm.smul.with.overflow.i63(i63, i63) nounwind readnone
75 %res = call { i63, i1 } @llvm.smul.with.overflow.i63(i63 4, i63 4611686018427387903)
76 %sum = extractvalue { i63, i1 } %res, 0
77 %overflow = extractvalue { i63, i1 } %res, 1
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/X86/
H A Dsmul-with-overflow.ll71 declare { i63, i1 } @llvm.smul.with.overflow.i63(i63, i63) nounwind readnone
75 %res = call { i63, i1 } @llvm.smul.with.overflow.i63(i63 4, i63 4611686018427387903)
76 %sum = extractvalue { i63, i1 } %res, 0
77 %overflow = extractvalue { i63, i1 } %res, 1
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/X86/
H A Dsmul-with-overflow.ll71 declare { i63, i1 } @llvm.smul.with.overflow.i63(i63, i63) nounwind readnone
75 %res = call { i63, i1 } @llvm.smul.with.overflow.i63(i63 4, i63 4611686018427387903)
76 %sum = extractvalue { i63, i1 } %res, 0
77 %overflow = extractvalue { i63, i1 } %res, 1
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/X86/
H A Dsmul-with-overflow.ll71 declare { i63, i1 } @llvm.smul.with.overflow.i63(i63, i63) nounwind readnone
75 %res = call { i63, i1 } @llvm.smul.with.overflow.i63(i63 4, i63 4611686018427387903)
76 %sum = extractvalue { i63, i1 } %res, 0
77 %overflow = extractvalue { i63, i1 } %res, 1
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/X86/
H A Dsmul-with-overflow.ll71 declare { i63, i1 } @llvm.smul.with.overflow.i63(i63, i63) nounwind readnone
75 %res = call { i63, i1 } @llvm.smul.with.overflow.i63(i63 4, i63 4611686018427387903)
76 %sum = extractvalue { i63, i1 } %res, 0
77 %overflow = extractvalue { i63, i1 } %res, 1
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/X86/
H A Dsmul-with-overflow.ll71 declare { i63, i1 } @llvm.smul.with.overflow.i63(i63, i63) nounwind readnone
75 %res = call { i63, i1 } @llvm.smul.with.overflow.i63(i63 4, i63 4611686018427387903)
76 %sum = extractvalue { i63, i1 } %res, 0
77 %overflow = extractvalue { i63, i1 } %res, 1
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/X86/
H A Dsmul-with-overflow.ll71 declare { i63, i1 } @llvm.smul.with.overflow.i63(i63, i63) nounwind readnone
75 %res = call { i63, i1 } @llvm.smul.with.overflow.i63(i63 4, i63 4611686018427387903)
76 %sum = extractvalue { i63, i1 } %res, 0
77 %overflow = extractvalue { i63, i1 } %res, 1
/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/X86/
H A Dsmul-with-overflow.ll71 declare { i63, i1 } @llvm.smul.with.overflow.i63(i63, i63) nounwind readnone
75 %res = call { i63, i1 } @llvm.smul.with.overflow.i63(i63 4, i63 4611686018427387903)
76 %sum = extractvalue { i63, i1 } %res, 0
77 %overflow = extractvalue { i63, i1 } %res, 1
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/X86/
H A Dsmul-with-overflow.ll71 declare { i63, i1 } @llvm.smul.with.overflow.i63(i63, i63) nounwind readnone
75 %res = call { i63, i1 } @llvm.smul.with.overflow.i63(i63 4, i63 4611686018427387903)
76 %sum = extractvalue { i63, i1 } %res, 0
77 %overflow = extractvalue { i63, i1 } %res, 1
/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/X86/
H A Dsmul-with-overflow.ll71 declare { i63, i1 } @llvm.smul.with.overflow.i63(i63, i63) nounwind readnone
75 %res = call { i63, i1 } @llvm.smul.with.overflow.i63(i63 4, i63 4611686018427387903)
76 %sum = extractvalue { i63, i1 } %res, 0
77 %overflow = extractvalue { i63, i1 } %res, 1
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/
H A Dmad_64_32.ll91 define i63 @mad_i64_i32_sextops_i32_i63(i32 %arg0, i32 %arg1, i63 %arg2) #0 {
92 %sext0 = sext i32 %arg0 to i63
93 %sext1 = sext i32 %arg1 to i63
94 %mul = mul i63 %sext0, %sext1
95 %mad = add i63 %mul, %arg2
96 ret i63 %mad
105 define i63 @mad_i64_i32_sextops_i31_i63(i31 %arg0, i31 %arg1, i63 %arg2) #0 {
106 %sext0 = sext i31 %arg0 to i63
108 %mul = mul i63 %sext0, %sext1
109 %mad = add i63 %mul, %arg2
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/
H A Dmad_64_32.ll91 define i63 @mad_i64_i32_sextops_i32_i63(i32 %arg0, i32 %arg1, i63 %arg2) #0 {
92 %sext0 = sext i32 %arg0 to i63
93 %sext1 = sext i32 %arg1 to i63
94 %mul = mul i63 %sext0, %sext1
95 %mad = add i63 %mul, %arg2
96 ret i63 %mad
105 define i63 @mad_i64_i32_sextops_i31_i63(i31 %arg0, i31 %arg1, i63 %arg2) #0 {
106 %sext0 = sext i31 %arg0 to i63
108 %mul = mul i63 %sext0, %sext1
109 %mad = add i63 %mul, %arg2
[all …]
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AMDGPU/
H A Dmad_64_32.ll91 define i63 @mad_i64_i32_sextops_i32_i63(i32 %arg0, i32 %arg1, i63 %arg2) #0 {
92 %sext0 = sext i32 %arg0 to i63
93 %sext1 = sext i32 %arg1 to i63
94 %mul = mul i63 %sext0, %sext1
95 %mad = add i63 %mul, %arg2
96 ret i63 %mad
105 define i63 @mad_i64_i32_sextops_i31_i63(i31 %arg0, i31 %arg1, i63 %arg2) #0 {
106 %sext0 = sext i31 %arg0 to i63
108 %mul = mul i63 %sext0, %sext1
109 %mad = add i63 %mul, %arg2
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dmad_64_32.ll91 define i63 @mad_i64_i32_sextops_i32_i63(i32 %arg0, i32 %arg1, i63 %arg2) #0 {
92 %sext0 = sext i32 %arg0 to i63
93 %sext1 = sext i32 %arg1 to i63
94 %mul = mul i63 %sext0, %sext1
95 %mad = add i63 %mul, %arg2
96 ret i63 %mad
105 define i63 @mad_i64_i32_sextops_i31_i63(i31 %arg0, i31 %arg1, i63 %arg2) #0 {
106 %sext0 = sext i31 %arg0 to i63
108 %mul = mul i63 %sext0, %sext1
109 %mad = add i63 %mul, %arg2
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/
H A Dmad_64_32.ll91 define i63 @mad_i64_i32_sextops_i32_i63(i32 %arg0, i32 %arg1, i63 %arg2) #0 {
92 %sext0 = sext i32 %arg0 to i63
93 %sext1 = sext i32 %arg1 to i63
94 %mul = mul i63 %sext0, %sext1
95 %mad = add i63 %mul, %arg2
96 ret i63 %mad
105 define i63 @mad_i64_i32_sextops_i31_i63(i31 %arg0, i31 %arg1, i63 %arg2) #0 {
106 %sext0 = sext i31 %arg0 to i63
108 %mul = mul i63 %sext0, %sext1
109 %mad = add i63 %mul, %arg2
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dmad_64_32.ll91 define i63 @mad_i64_i32_sextops_i32_i63(i32 %arg0, i32 %arg1, i63 %arg2) #0 {
92 %sext0 = sext i32 %arg0 to i63
93 %sext1 = sext i32 %arg1 to i63
94 %mul = mul i63 %sext0, %sext1
95 %mad = add i63 %mul, %arg2
96 ret i63 %mad
105 define i63 @mad_i64_i32_sextops_i31_i63(i31 %arg0, i31 %arg1, i63 %arg2) #0 {
106 %sext0 = sext i31 %arg0 to i63
108 %mul = mul i63 %sext0, %sext1
109 %mad = add i63 %mul, %arg2
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/
H A Dmad_64_32.ll91 define i63 @mad_i64_i32_sextops_i32_i63(i32 %arg0, i32 %arg1, i63 %arg2) #0 {
92 %sext0 = sext i32 %arg0 to i63
93 %sext1 = sext i32 %arg1 to i63
94 %mul = mul i63 %sext0, %sext1
95 %mad = add i63 %mul, %arg2
96 ret i63 %mad
105 define i63 @mad_i64_i32_sextops_i31_i63(i31 %arg0, i31 %arg1, i63 %arg2) #0 {
106 %sext0 = sext i31 %arg0 to i63
108 %mul = mul i63 %sext0, %sext1
109 %mad = add i63 %mul, %arg2
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/
H A Dmad_64_32.ll91 define i63 @mad_i64_i32_sextops_i32_i63(i32 %arg0, i32 %arg1, i63 %arg2) #0 {
92 %sext0 = sext i32 %arg0 to i63
93 %sext1 = sext i32 %arg1 to i63
94 %mul = mul i63 %sext0, %sext1
95 %mad = add i63 %mul, %arg2
96 ret i63 %mad
105 define i63 @mad_i64_i32_sextops_i31_i63(i31 %arg0, i31 %arg1, i63 %arg2) #0 {
106 %sext0 = sext i31 %arg0 to i63
108 %mul = mul i63 %sext0, %sext1
109 %mad = add i63 %mul, %arg2
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dmad_64_32.ll91 define i63 @mad_i64_i32_sextops_i32_i63(i32 %arg0, i32 %arg1, i63 %arg2) #0 {
92 %sext0 = sext i32 %arg0 to i63
93 %sext1 = sext i32 %arg1 to i63
94 %mul = mul i63 %sext0, %sext1
95 %mad = add i63 %mul, %arg2
96 ret i63 %mad
105 define i63 @mad_i64_i32_sextops_i31_i63(i31 %arg0, i31 %arg1, i63 %arg2) #0 {
106 %sext0 = sext i31 %arg0 to i63
108 %mul = mul i63 %sext0, %sext1
109 %mad = add i63 %mul, %arg2
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dmad_64_32.ll91 define i63 @mad_i64_i32_sextops_i32_i63(i32 %arg0, i32 %arg1, i63 %arg2) #0 {
92 %sext0 = sext i32 %arg0 to i63
93 %sext1 = sext i32 %arg1 to i63
94 %mul = mul i63 %sext0, %sext1
95 %mad = add i63 %mul, %arg2
96 ret i63 %mad
105 define i63 @mad_i64_i32_sextops_i31_i63(i31 %arg0, i31 %arg1, i63 %arg2) #0 {
106 %sext0 = sext i31 %arg0 to i63
108 %mul = mul i63 %sext0, %sext1
109 %mad = add i63 %mul, %arg2
[all …]

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