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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/PowerPC/
H A Dppc32-lshrti3.ll12 %.promoted = load i72, i72* inttoptr (i32 1 to i72*), align 4
16 %bf.set3 = phi i72 [ %bf.set, %while.cond ], [ %.promoted, %entry ]
17 %bf.lshr = lshr i72 %bf.set3, 40
18 %bf.lshr.tr = trunc i72 %bf.lshr to i32
21 %0 = zext i32 %dec to i72
22 %bf.value = shl nuw i72 %0, 40
23 %bf.shl = and i72 %bf.value, 72056494526300160
24 %bf.clear2 = and i72 %bf.set3, -72056494526300161
25 %bf.set = or i72 %bf.shl, %bf.clear2
30 %bf.set.lcssa = phi i72 [ %bf.set, %while.cond ]
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/PowerPC/
H A Dppc32-lshrti3.ll12 %.promoted = load i72, i72* inttoptr (i32 1 to i72*), align 4
16 %bf.set3 = phi i72 [ %bf.set, %while.cond ], [ %.promoted, %entry ]
17 %bf.lshr = lshr i72 %bf.set3, 40
18 %bf.lshr.tr = trunc i72 %bf.lshr to i32
21 %0 = zext i32 %dec to i72
22 %bf.value = shl nuw i72 %0, 40
23 %bf.shl = and i72 %bf.value, 72056494526300160
24 %bf.clear2 = and i72 %bf.set3, -72056494526300161
25 %bf.set = or i72 %bf.shl, %bf.clear2
30 %bf.set.lcssa = phi i72 [ %bf.set, %while.cond ]
[all …]
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/PowerPC/
H A Dppc32-lshrti3.ll12 %.promoted = load i72, i72* inttoptr (i32 1 to i72*), align 4
16 %bf.set3 = phi i72 [ %bf.set, %while.cond ], [ %.promoted, %entry ]
17 %bf.lshr = lshr i72 %bf.set3, 40
18 %bf.lshr.tr = trunc i72 %bf.lshr to i32
21 %0 = zext i32 %dec to i72
22 %bf.value = shl nuw i72 %0, 40
23 %bf.shl = and i72 %bf.value, 72056494526300160
24 %bf.clear2 = and i72 %bf.set3, -72056494526300161
25 %bf.set = or i72 %bf.shl, %bf.clear2
30 %bf.set.lcssa = phi i72 [ %bf.set, %while.cond ]
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/PowerPC/
H A Dppc32-lshrti3.ll12 %.promoted = load i72, i72* inttoptr (i32 1 to i72*), align 4
16 %bf.set3 = phi i72 [ %bf.set, %while.cond ], [ %.promoted, %entry ]
17 %bf.lshr = lshr i72 %bf.set3, 40
18 %bf.lshr.tr = trunc i72 %bf.lshr to i32
21 %0 = zext i32 %dec to i72
22 %bf.value = shl nuw i72 %0, 40
23 %bf.shl = and i72 %bf.value, 72056494526300160
24 %bf.clear2 = and i72 %bf.set3, -72056494526300161
25 %bf.set = or i72 %bf.shl, %bf.clear2
30 %bf.set.lcssa = phi i72 [ %bf.set, %while.cond ]
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dppc32-lshrti3.ll12 %.promoted = load i72, i72* inttoptr (i32 1 to i72*), align 4
16 %bf.set3 = phi i72 [ %bf.set, %while.cond ], [ %.promoted, %entry ]
17 %bf.lshr = lshr i72 %bf.set3, 40
18 %bf.lshr.tr = trunc i72 %bf.lshr to i32
21 %0 = zext i32 %dec to i72
22 %bf.value = shl nuw i72 %0, 40
23 %bf.shl = and i72 %bf.value, 72056494526300160
24 %bf.clear2 = and i72 %bf.set3, -72056494526300161
25 %bf.set = or i72 %bf.shl, %bf.clear2
30 %bf.set.lcssa = phi i72 [ %bf.set, %while.cond ]
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dppc32-lshrti3.ll12 %.promoted = load i72, i72* inttoptr (i32 1 to i72*), align 4
16 %bf.set3 = phi i72 [ %bf.set, %while.cond ], [ %.promoted, %entry ]
17 %bf.lshr = lshr i72 %bf.set3, 40
18 %bf.lshr.tr = trunc i72 %bf.lshr to i32
21 %0 = zext i32 %dec to i72
22 %bf.value = shl nuw i72 %0, 40
23 %bf.shl = and i72 %bf.value, 72056494526300160
24 %bf.clear2 = and i72 %bf.set3, -72056494526300161
25 %bf.set = or i72 %bf.shl, %bf.clear2
30 %bf.set.lcssa = phi i72 [ %bf.set, %while.cond ]
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/PowerPC/
H A Dppc32-lshrti3.ll12 %.promoted = load i72, i72* inttoptr (i32 1 to i72*), align 4
16 %bf.set3 = phi i72 [ %bf.set, %while.cond ], [ %.promoted, %entry ]
17 %bf.lshr = lshr i72 %bf.set3, 40
18 %bf.lshr.tr = trunc i72 %bf.lshr to i32
21 %0 = zext i32 %dec to i72
22 %bf.value = shl nuw i72 %0, 40
23 %bf.shl = and i72 %bf.value, 72056494526300160
24 %bf.clear2 = and i72 %bf.set3, -72056494526300161
25 %bf.set = or i72 %bf.shl, %bf.clear2
30 %bf.set.lcssa = phi i72 [ %bf.set, %while.cond ]
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dppc32-lshrti3.ll12 %.promoted = load i72, i72* inttoptr (i32 1 to i72*), align 4
16 %bf.set3 = phi i72 [ %bf.set, %while.cond ], [ %.promoted, %entry ]
17 %bf.lshr = lshr i72 %bf.set3, 40
18 %bf.lshr.tr = trunc i72 %bf.lshr to i32
21 %0 = zext i32 %dec to i72
22 %bf.value = shl nuw i72 %0, 40
23 %bf.shl = and i72 %bf.value, 72056494526300160
24 %bf.clear2 = and i72 %bf.set3, -72056494526300161
25 %bf.set = or i72 %bf.shl, %bf.clear2
30 %bf.set.lcssa = phi i72 [ %bf.set, %while.cond ]
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dppc32-lshrti3.ll12 %.promoted = load i72, i72* inttoptr (i32 1 to i72*), align 4
16 %bf.set3 = phi i72 [ %bf.set, %while.cond ], [ %.promoted, %entry ]
17 %bf.lshr = lshr i72 %bf.set3, 40
18 %bf.lshr.tr = trunc i72 %bf.lshr to i32
21 %0 = zext i32 %dec to i72
22 %bf.value = shl nuw i72 %0, 40
23 %bf.shl = and i72 %bf.value, 72056494526300160
24 %bf.clear2 = and i72 %bf.set3, -72056494526300161
25 %bf.set = or i72 %bf.shl, %bf.clear2
30 %bf.set.lcssa = phi i72 [ %bf.set, %while.cond ]
[all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/PowerPC/
H A Dppc32-lshrti3.ll12 %.promoted = load i72, i72* inttoptr (i32 1 to i72*), align 4
16 %bf.set3 = phi i72 [ %bf.set, %while.cond ], [ %.promoted, %entry ]
17 %bf.lshr = lshr i72 %bf.set3, 40
18 %bf.lshr.tr = trunc i72 %bf.lshr to i32
21 %0 = zext i32 %dec to i72
22 %bf.value = shl nuw i72 %0, 40
23 %bf.shl = and i72 %bf.value, 72056494526300160
24 %bf.clear2 = and i72 %bf.set3, -72056494526300161
25 %bf.set = or i72 %bf.shl, %bf.clear2
30 %bf.set.lcssa = phi i72 [ %bf.set, %while.cond ]
[all …]
/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/PowerPC/
H A Dppc32-lshrti3.ll12 %.promoted = load i72, i72* inttoptr (i32 1 to i72*), align 4
16 %bf.set3 = phi i72 [ %bf.set, %while.cond ], [ %.promoted, %entry ]
17 %bf.lshr = lshr i72 %bf.set3, 40
18 %bf.lshr.tr = trunc i72 %bf.lshr to i32
21 %0 = zext i32 %dec to i72
22 %bf.value = shl nuw i72 %0, 40
23 %bf.shl = and i72 %bf.value, 72056494526300160
24 %bf.clear2 = and i72 %bf.set3, -72056494526300161
25 %bf.set = or i72 %bf.shl, %bf.clear2
30 %bf.set.lcssa = phi i72 [ %bf.set, %while.cond ]
[all …]
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/PowerPC/
H A Dppc32-lshrti3.ll12 %.promoted = load i72, i72* inttoptr (i32 1 to i72*), align 4
16 %bf.set3 = phi i72 [ %bf.set, %while.cond ], [ %.promoted, %entry ]
17 %bf.lshr = lshr i72 %bf.set3, 40
18 %bf.lshr.tr = trunc i72 %bf.lshr to i32
21 %0 = zext i32 %dec to i72
22 %bf.value = shl nuw i72 %0, 40
23 %bf.shl = and i72 %bf.value, 72056494526300160
24 %bf.clear2 = and i72 %bf.set3, -72056494526300161
25 %bf.set = or i72 %bf.shl, %bf.clear2
30 %bf.set.lcssa = phi i72 [ %bf.set, %while.cond ]
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/PowerPC/
H A Dppc32-lshrti3.ll12 %.promoted = load i72, i72* inttoptr (i32 1 to i72*), align 4
16 %bf.set3 = phi i72 [ %bf.set, %while.cond ], [ %.promoted, %entry ]
17 %bf.lshr = lshr i72 %bf.set3, 40
18 %bf.lshr.tr = trunc i72 %bf.lshr to i32
21 %0 = zext i32 %dec to i72
22 %bf.value = shl nuw i72 %0, 40
23 %bf.shl = and i72 %bf.value, 72056494526300160
24 %bf.clear2 = and i72 %bf.set3, -72056494526300161
25 %bf.set = or i72 %bf.shl, %bf.clear2
30 %bf.set.lcssa = phi i72 [ %bf.set, %while.cond ]
[all …]
/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/PowerPC/
H A Dppc32-lshrti3.ll12 %.promoted = load i72, i72* inttoptr (i32 1 to i72*), align 4
16 %bf.set3 = phi i72 [ %bf.set, %while.cond ], [ %.promoted, %entry ]
17 %bf.lshr = lshr i72 %bf.set3, 40
18 %bf.lshr.tr = trunc i72 %bf.lshr to i32
21 %0 = zext i32 %dec to i72
22 %bf.value = shl nuw i72 %0, 40
23 %bf.shl = and i72 %bf.value, 72056494526300160
24 %bf.clear2 = and i72 %bf.set3, -72056494526300161
25 %bf.set = or i72 %bf.shl, %bf.clear2
30 %bf.set.lcssa = phi i72 [ %bf.set, %while.cond ]
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/PowerPC/
H A Dppc32-lshrti3.ll12 %.promoted = load i72, i72* inttoptr (i32 1 to i72*), align 4
16 %bf.set3 = phi i72 [ %bf.set, %while.cond ], [ %.promoted, %entry ]
17 %bf.lshr = lshr i72 %bf.set3, 40
18 %bf.lshr.tr = trunc i72 %bf.lshr to i32
21 %0 = zext i32 %dec to i72
22 %bf.value = shl nuw i72 %0, 40
23 %bf.shl = and i72 %bf.value, 72056494526300160
24 %bf.clear2 = and i72 %bf.set3, -72056494526300161
25 %bf.set = or i72 %bf.shl, %bf.clear2
30 %bf.set.lcssa = phi i72 [ %bf.set, %while.cond ]
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/Analysis/CostModel/SystemZ/
H A Dhuge-immediates.ll6 define i32 @fun0(i72* %Src) {
7 %L = load i72, i72* %Src
8 %B = icmp ult i72 %L, 166153499473114484112
14 define i32 @fun1(i72* %Src, i72* %Dst) {
15 %L = load i72, i72* %Src
16 store i72 %L, i72* %Dst
17 %B = icmp ult i72 %L, 166153499473114484112
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/Analysis/CostModel/SystemZ/
H A Dhuge-immediates.ll6 define i32 @fun0(i72* %Src) {
7 %L = load i72, i72* %Src
8 %B = icmp ult i72 %L, 166153499473114484112
14 define i32 @fun1(i72* %Src, i72* %Dst) {
15 %L = load i72, i72* %Src
16 store i72 %L, i72* %Dst
17 %B = icmp ult i72 %L, 166153499473114484112
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/Analysis/CostModel/SystemZ/
H A Dhuge-immediates.ll6 define i32 @fun0(i72* %Src) {
7 %L = load i72, i72* %Src
8 %B = icmp ult i72 %L, 166153499473114484112
14 define i32 @fun1(i72* %Src, i72* %Dst) {
15 %L = load i72, i72* %Src
16 store i72 %L, i72* %Dst
17 %B = icmp ult i72 %L, 166153499473114484112
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/Analysis/CostModel/SystemZ/
H A Dhuge-immediates.ll6 define i32 @fun0(i72* %Src) {
7 %L = load i72, i72* %Src
8 %B = icmp ult i72 %L, 166153499473114484112
14 define i32 @fun1(i72* %Src, i72* %Dst) {
15 %L = load i72, i72* %Src
16 store i72 %L, i72* %Dst
17 %B = icmp ult i72 %L, 166153499473114484112
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/Analysis/CostModel/SystemZ/
H A Dhuge-immediates.ll6 define i32 @fun0(i72* %Src) {
7 %L = load i72, i72* %Src
8 %B = icmp ult i72 %L, 166153499473114484112
14 define i32 @fun1(i72* %Src, i72* %Dst) {
15 %L = load i72, i72* %Src
16 store i72 %L, i72* %Dst
17 %B = icmp ult i72 %L, 166153499473114484112
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/Analysis/CostModel/SystemZ/
H A Dhuge-immediates.ll6 define i32 @fun0(i72* %Src) {
7 %L = load i72, i72* %Src
8 %B = icmp ult i72 %L, 166153499473114484112
14 define i32 @fun1(i72* %Src, i72* %Dst) {
15 %L = load i72, i72* %Src
16 store i72 %L, i72* %Dst
17 %B = icmp ult i72 %L, 166153499473114484112
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/Analysis/CostModel/SystemZ/
H A Dhuge-immediates.ll6 define i32 @fun0(i72* %Src) {
7 %L = load i72, i72* %Src
8 %B = icmp ult i72 %L, 166153499473114484112
14 define i32 @fun1(i72* %Src, i72* %Dst) {
15 %L = load i72, i72* %Src
16 store i72 %L, i72* %Dst
17 %B = icmp ult i72 %L, 166153499473114484112
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/Analysis/CostModel/SystemZ/
H A Dhuge-immediates.ll6 define i32 @fun0(i72* %Src) {
7 %L = load i72, i72* %Src
8 %B = icmp ult i72 %L, 166153499473114484112
14 define i32 @fun1(i72* %Src, i72* %Dst) {
15 %L = load i72, i72* %Src
16 store i72 %L, i72* %Dst
17 %B = icmp ult i72 %L, 166153499473114484112
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/Transforms/SLPVectorizer/AArch64/
H A Dminimum-sizes.ll52 ; CHECK-NEXT: [[BF_CLEAR13:%.*]] = and i72 [[D]], -576460748008464384
53 ; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[SUB]] to i72
54 ; CHECK-NEXT: [[BF_VALUE15:%.*]] = and i72 [[TMP1]], 8191
55 ; CHECK-NEXT: [[BF_CLEAR16:%.*]] = or i72 [[BF_VALUE15]], [[BF_CLEAR13]]
56 ; CHECK-NEXT: [[BF_SET17]] = or i72 [[BF_CLEAR16]], undef
69 %d = phi i72 [ 576507472957710340, %for.ph ], [ %bf.set17, %for.body ]
71 %bf.clear13 = and i72 %d, -576460748008464384
72 %1 = zext i32 %sub to i72
73 %bf.value15 = and i72 %1, 8191
74 %bf.clear16 = or i72 %bf.value15, %bf.clear13
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/test/Transforms/SLPVectorizer/AArch64/
H A Dminimum-sizes.ll52 ; CHECK-NEXT: [[BF_CLEAR13:%.*]] = and i72 [[D]], -576460748008464384
53 ; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[SUB]] to i72
54 ; CHECK-NEXT: [[BF_VALUE15:%.*]] = and i72 [[TMP1]], 8191
55 ; CHECK-NEXT: [[BF_CLEAR16:%.*]] = or i72 [[BF_VALUE15]], [[BF_CLEAR13]]
56 ; CHECK-NEXT: [[BF_SET17]] = or i72 [[BF_CLEAR16]], undef
69 %d = phi i72 [ 576507472957710340, %for.ph ], [ %bf.set17, %for.body ]
71 %bf.clear13 = and i72 %d, -576460748008464384
72 %1 = zext i32 %sub to i72
73 %bf.value15 = and i72 %1, 8191
74 %bf.clear16 = or i72 %bf.value15, %bf.clear13
[all …]

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