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/dports/devel/simde/simde-0.7.2/simde/x86/avx512/
H A Dextract.h46 return a_.m128[imm8 & 3]; in simde_mm512_extractf32x4_ps()
60 #define simde_mm512_extractf32x4_ps(a, imm8) _mm512_extractf32x4_ps(a, imm8) argument
64 #define _mm512_extractf32x4_ps(a, imm8) simde_mm512_extractf32x4_ps(a, imm8) argument
93 return a_.m256d[imm8 & 1]; in simde_mm512_extractf64x4_pd()
96 #define simde_mm512_extractf64x4_pd(a, imm8) _mm512_extractf64x4_pd(a, imm8) argument
100 #define _mm512_extractf64x4_pd(a, imm8) simde_mm512_extractf64x4_pd(a, imm8) argument
129 return a_.m128i[imm8 & 3]; in simde_mm512_extracti32x4_epi32()
132 #define simde_mm512_extracti32x4_epi32(a, imm8) _mm512_extracti32x4_epi32(a, imm8) argument
136 #define _mm512_extracti32x4_epi32(a, imm8) simde_mm512_extracti32x4_epi32(a, imm8) argument
168 #define simde_mm512_extracti64x4_epi64(a, imm8) _mm512_extracti64x4_epi64(a, imm8) argument
[all …]
H A Dinsert.h44 a_.m128[imm8 & 3] = b; in simde_mm512_insertf32x4()
49 #define simde_mm512_insertf32x4(a, b, imm8) _mm512_insertf32x4(a, b, imm8) argument
53 #define _mm512_insertf32x4(a, b, imm8) simde_mm512_insertf32x4(a, b, imm8) argument
82 a_.m256d[imm8 & 1] = b; in simde_mm512_insertf64x4()
87 #define simde_mm512_insertf64x4(a, b, imm8) _mm512_insertf64x4(a, b, imm8) argument
91 #define _mm512_insertf64x4(a, b, imm8) simde_mm512_insertf64x4(a, b, imm8) argument
120 a_.m128i[imm8 & 3] = b; in simde_mm512_inserti32x4()
125 #define simde_mm512_inserti32x4(a, b, imm8) _mm512_inserti32x4(a, b, imm8) argument
129 #define _mm512_inserti32x4(a, b, imm8) simde_mm512_inserti32x4(a, b, imm8) argument
163 #define simde_mm512_inserti64x4(a, b, imm8) _mm512_inserti64x4(a, b, imm8) argument
[all …]
H A Dshuffle.h106 r_.m128i[0] = a_.m128i[ imm8 & 1]; in simde_mm256_shuffle_i32x4()
107 r_.m128i[1] = b_.m128i[(imm8 >> 1) & 1]; in simde_mm256_shuffle_i32x4()
112 #define simde_mm256_shuffle_i32x4(a, b, imm8) _mm256_shuffle_i32x4(a, b, imm8) argument
116 #define _mm256_shuffle_i32x4(a, b, imm8) simde_mm256_shuffle_i32x4(a, b, imm8) argument
126 #define simde_mm256_shuffle_i64x2(a, b, imm8) simde_mm256_shuffle_i32x4(a, b, imm8) argument
143 r_.m128i[0] = a_.m128i[ imm8 & 3]; in simde_mm512_shuffle_i32x4()
144 r_.m128i[1] = a_.m128i[(imm8 >> 2) & 3]; in simde_mm512_shuffle_i32x4()
145 r_.m128i[2] = b_.m128i[(imm8 >> 4) & 3]; in simde_mm512_shuffle_i32x4()
151 #define simde_mm512_shuffle_i32x4(a, b, imm8) _mm512_shuffle_i32x4(a, b, imm8) argument
155 #define _mm512_shuffle_i32x4(a, b, imm8) simde_mm512_shuffle_i32x4(a, b, imm8) argument
[all …]
H A Dsrli.h65 r_.u16[i] = a_.u16[i] >> imm8; in simde_mm512_srli_epi16()
73 #define simde_mm512_srli_epi16(a, imm8) _mm512_srli_epi16(a, imm8) argument
77 #define _mm512_srli_epi16(a, imm8) simde_mm512_srli_epi16(a, imm8) argument
105 if (imm8 > 31) { in simde_mm512_srli_epi32()
109 r_.u32 = a_.u32 >> imm8; in simde_mm512_srli_epi32()
113 r_.u32[i] = a_.u32[i] >> imm8; in simde_mm512_srli_epi32()
124 #define _mm512_srli_epi32(a, imm8) simde_mm512_srli_epi32(a, imm8) argument
155 if (imm8 > 63) { in simde_mm512_srli_epi64()
159 r_.u64 = a_.u64 >> imm8; in simde_mm512_srli_epi64()
163 r_.u64[i] = a_.u64[i] >> imm8; in simde_mm512_srli_epi64()
[all …]
H A Dslli.h44 SIMDE_REQUIRE_RANGE(imm8, 0, 255) { in simde_mm512_slli_epi16()
59 if(imm8 < 16) in simde_mm512_slli_epi16()
66 r_.i16[i] = (imm8 < 16) ? HEDLEY_STATIC_CAST(int16_t, a_.i16[i] << (imm8 & 0xff)) : 0; in simde_mm512_slli_epi16()
75 #define _mm512_slli_epi16(a, imm8) simde_mm512_slli_epi16(a, imm8) argument
99 if (imm8 > 31) { in simde_mm512_slli_epi32()
111 r_.u32 = a_.u32 << imm8; in simde_mm512_slli_epi32()
115 r_.u32[i] = a_.u32[i] << imm8; in simde_mm512_slli_epi32()
125 #define _mm512_slli_epi32(a, imm8) simde_mm512_slli_epi32(a, imm8) argument
147 if (imm8 > 63) { in simde_mm512_slli_epi64()
159 r_.u64 = a_.u64 << imm8; in simde_mm512_slli_epi64()
[all …]
/dports/biology/bowtie2/simde-no-tests-f6a0b3b/x86/avx512/
H A Dextract.h46 return a_.m128[imm8 & 3]; in simde_mm512_extractf32x4_ps()
60 #define simde_mm512_extractf32x4_ps(a, imm8) _mm512_extractf32x4_ps(a, imm8) argument
64 #define _mm512_extractf32x4_ps(a, imm8) simde_mm512_extractf32x4_ps(a, imm8) argument
93 return a_.m256d[imm8 & 1]; in simde_mm512_extractf64x4_pd()
96 #define simde_mm512_extractf64x4_pd(a, imm8) _mm512_extractf64x4_pd(a, imm8) argument
100 #define _mm512_extractf64x4_pd(a, imm8) simde_mm512_extractf64x4_pd(a, imm8) argument
129 return a_.m128i[imm8 & 3]; in simde_mm512_extracti32x4_epi32()
132 #define simde_mm512_extracti32x4_epi32(a, imm8) _mm512_extracti32x4_epi32(a, imm8) argument
136 #define _mm512_extracti32x4_epi32(a, imm8) simde_mm512_extracti32x4_epi32(a, imm8) argument
168 #define simde_mm512_extracti64x4_epi64(a, imm8) _mm512_extracti64x4_epi64(a, imm8) argument
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H A Dinsert.h44 a_.m128[imm8 & 3] = b; in simde_mm512_insertf32x4()
49 #define simde_mm512_insertf32x4(a, b, imm8) _mm512_insertf32x4(a, b, imm8) argument
53 #define _mm512_insertf32x4(a, b, imm8) simde_mm512_insertf32x4(a, b, imm8) argument
82 a_.m256d[imm8 & 1] = b; in simde_mm512_insertf64x4()
87 #define simde_mm512_insertf64x4(a, b, imm8) _mm512_insertf64x4(a, b, imm8) argument
91 #define _mm512_insertf64x4(a, b, imm8) simde_mm512_insertf64x4(a, b, imm8) argument
120 a_.m128i[imm8 & 3] = b; in simde_mm512_inserti32x4()
125 #define simde_mm512_inserti32x4(a, b, imm8) _mm512_inserti32x4(a, b, imm8) argument
129 #define _mm512_inserti32x4(a, b, imm8) simde_mm512_inserti32x4(a, b, imm8) argument
163 #define simde_mm512_inserti64x4(a, b, imm8) _mm512_inserti64x4(a, b, imm8) argument
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H A Dshuffle.h106 r_.m128i[0] = a_.m128i[ imm8 & 1]; in simde_mm256_shuffle_i32x4()
107 r_.m128i[1] = b_.m128i[(imm8 >> 1) & 1]; in simde_mm256_shuffle_i32x4()
112 #define simde_mm256_shuffle_i32x4(a, b, imm8) _mm256_shuffle_i32x4(a, b, imm8) argument
116 #define _mm256_shuffle_i32x4(a, b, imm8) simde_mm256_shuffle_i32x4(a, b, imm8) argument
126 #define simde_mm256_shuffle_i64x2(a, b, imm8) simde_mm256_shuffle_i32x4(a, b, imm8) argument
143 r_.m128i[0] = a_.m128i[ imm8 & 3]; in simde_mm512_shuffle_i32x4()
144 r_.m128i[1] = a_.m128i[(imm8 >> 2) & 3]; in simde_mm512_shuffle_i32x4()
145 r_.m128i[2] = b_.m128i[(imm8 >> 4) & 3]; in simde_mm512_shuffle_i32x4()
151 #define simde_mm512_shuffle_i32x4(a, b, imm8) _mm512_shuffle_i32x4(a, b, imm8) argument
155 #define _mm512_shuffle_i32x4(a, b, imm8) simde_mm512_shuffle_i32x4(a, b, imm8) argument
[all …]
H A Dsrli.h65 r_.u16[i] = a_.u16[i] >> imm8; in simde_mm512_srli_epi16()
73 #define simde_mm512_srli_epi16(a, imm8) _mm512_srli_epi16(a, imm8) argument
77 #define _mm512_srli_epi16(a, imm8) simde_mm512_srli_epi16(a, imm8) argument
105 if (imm8 > 31) { in simde_mm512_srli_epi32()
109 r_.u32 = a_.u32 >> imm8; in simde_mm512_srli_epi32()
113 r_.u32[i] = a_.u32[i] >> imm8; in simde_mm512_srli_epi32()
124 #define _mm512_srli_epi32(a, imm8) simde_mm512_srli_epi32(a, imm8) argument
155 if (imm8 > 63) { in simde_mm512_srli_epi64()
159 r_.u64 = a_.u64 >> imm8; in simde_mm512_srli_epi64()
163 r_.u64[i] = a_.u64[i] >> imm8; in simde_mm512_srli_epi64()
[all …]
H A Dslli.h44 SIMDE_REQUIRE_RANGE(imm8, 0, 255) { in simde_mm512_slli_epi16()
59 if(imm8 < 16) in simde_mm512_slli_epi16()
66 r_.i16[i] = (imm8 < 16) ? HEDLEY_STATIC_CAST(int16_t, a_.i16[i] << (imm8 & 0xff)) : 0; in simde_mm512_slli_epi16()
75 #define _mm512_slli_epi16(a, imm8) simde_mm512_slli_epi16(a, imm8) argument
99 if (imm8 > 31) { in simde_mm512_slli_epi32()
111 r_.u32 = a_.u32 << imm8; in simde_mm512_slli_epi32()
115 r_.u32[i] = a_.u32[i] << imm8; in simde_mm512_slli_epi32()
125 #define _mm512_slli_epi32(a, imm8) simde_mm512_slli_epi32(a, imm8) argument
147 if (imm8 > 63) { in simde_mm512_slli_epi64()
159 r_.u64 = a_.u64 << imm8; in simde_mm512_slli_epi64()
[all …]
/dports/biology/mmseqs2/MMseqs2-13-45111/lib/simde/simde/x86/avx512/
H A Dextract.h46 return a_.m128[imm8 & 3]; in simde_mm512_extractf32x4_ps()
60 #define simde_mm512_extractf32x4_ps(a, imm8) _mm512_extractf32x4_ps(a, imm8) argument
64 #define _mm512_extractf32x4_ps(a, imm8) simde_mm512_extractf32x4_ps(a, imm8) argument
93 return a_.m256d[imm8 & 1]; in simde_mm512_extractf64x4_pd()
96 #define simde_mm512_extractf64x4_pd(a, imm8) _mm512_extractf64x4_pd(a, imm8) argument
100 #define _mm512_extractf64x4_pd(a, imm8) simde_mm512_extractf64x4_pd(a, imm8) argument
129 return a_.m128i[imm8 & 3]; in simde_mm512_extracti32x4_epi32()
132 #define simde_mm512_extracti32x4_epi32(a, imm8) _mm512_extracti32x4_epi32(a, imm8) argument
136 #define _mm512_extracti32x4_epi32(a, imm8) simde_mm512_extracti32x4_epi32(a, imm8) argument
168 #define simde_mm512_extracti64x4_epi64(a, imm8) _mm512_extracti64x4_epi64(a, imm8) argument
[all …]
H A Dinsert.h44 a_.m128[imm8 & 3] = b; in simde_mm512_insertf32x4()
49 #define simde_mm512_insertf32x4(a, b, imm8) _mm512_insertf32x4(a, b, imm8) argument
53 #define _mm512_insertf32x4(a, b, imm8) simde_mm512_insertf32x4(a, b, imm8) argument
82 a_.m256d[imm8 & 1] = b; in simde_mm512_insertf64x4()
87 #define simde_mm512_insertf64x4(a, b, imm8) _mm512_insertf64x4(a, b, imm8) argument
91 #define _mm512_insertf64x4(a, b, imm8) simde_mm512_insertf64x4(a, b, imm8) argument
120 a_.m128i[imm8 & 3] = b; in simde_mm512_inserti32x4()
125 #define simde_mm512_inserti32x4(a, b, imm8) _mm512_inserti32x4(a, b, imm8) argument
129 #define _mm512_inserti32x4(a, b, imm8) simde_mm512_inserti32x4(a, b, imm8) argument
163 #define simde_mm512_inserti64x4(a, b, imm8) _mm512_inserti64x4(a, b, imm8) argument
[all …]
H A Dshuffle.h106 r_.m128i[0] = a_.m128i[ imm8 & 1]; in simde_mm256_shuffle_i32x4()
107 r_.m128i[1] = b_.m128i[(imm8 >> 1) & 1]; in simde_mm256_shuffle_i32x4()
112 #define simde_mm256_shuffle_i32x4(a, b, imm8) _mm256_shuffle_i32x4(a, b, imm8) argument
116 #define _mm256_shuffle_i32x4(a, b, imm8) simde_mm256_shuffle_i32x4(a, b, imm8) argument
126 #define simde_mm256_shuffle_i64x2(a, b, imm8) simde_mm256_shuffle_i32x4(a, b, imm8) argument
143 r_.m128i[0] = a_.m128i[ imm8 & 3]; in simde_mm512_shuffle_i32x4()
144 r_.m128i[1] = a_.m128i[(imm8 >> 2) & 3]; in simde_mm512_shuffle_i32x4()
145 r_.m128i[2] = b_.m128i[(imm8 >> 4) & 3]; in simde_mm512_shuffle_i32x4()
151 #define simde_mm512_shuffle_i32x4(a, b, imm8) _mm512_shuffle_i32x4(a, b, imm8) argument
155 #define _mm512_shuffle_i32x4(a, b, imm8) simde_mm512_shuffle_i32x4(a, b, imm8) argument
[all …]
H A Dsrli.h65 r_.u16[i] = a_.u16[i] >> imm8; in simde_mm512_srli_epi16()
73 #define simde_mm512_srli_epi16(a, imm8) _mm512_srli_epi16(a, imm8) argument
77 #define _mm512_srli_epi16(a, imm8) simde_mm512_srli_epi16(a, imm8) argument
105 if (imm8 > 31) { in simde_mm512_srli_epi32()
109 r_.u32 = a_.u32 >> imm8; in simde_mm512_srli_epi32()
113 r_.u32[i] = a_.u32[i] >> imm8; in simde_mm512_srli_epi32()
124 #define _mm512_srli_epi32(a, imm8) simde_mm512_srli_epi32(a, imm8) argument
155 if (imm8 > 63) { in simde_mm512_srli_epi64()
159 r_.u64 = a_.u64 >> imm8; in simde_mm512_srli_epi64()
163 r_.u64[i] = a_.u64[i] >> imm8; in simde_mm512_srli_epi64()
[all …]
H A Dslli.h44 SIMDE_REQUIRE_RANGE(imm8, 0, 255) { in simde_mm512_slli_epi16()
59 if(imm8 < 16) in simde_mm512_slli_epi16()
66 r_.i16[i] = (imm8 < 16) ? HEDLEY_STATIC_CAST(int16_t, a_.i16[i] << (imm8 & 0xff)) : 0; in simde_mm512_slli_epi16()
75 #define _mm512_slli_epi16(a, imm8) simde_mm512_slli_epi16(a, imm8) argument
99 if (imm8 > 31) { in simde_mm512_slli_epi32()
111 r_.u32 = a_.u32 << imm8; in simde_mm512_slli_epi32()
115 r_.u32[i] = a_.u32[i] << imm8; in simde_mm512_slli_epi32()
125 #define _mm512_slli_epi32(a, imm8) simde_mm512_slli_epi32(a, imm8) argument
147 if (imm8 > 63) { in simde_mm512_slli_epi64()
159 r_.u64 = a_.u64 << imm8; in simde_mm512_slli_epi64()
[all …]
/dports/devel/valgrind-lts/valgrind-dragonfly-dragonfly/none/tests/amd64/
H A Dinsn_pclmulqdq.def1 pclmulqdq imm8[0] xmm.uq[0x00017004200ab0cd,0xc000b802f6b31753] xmm.uq[0xa0005c0252074a9a,0x50002e0…
2 pclmulqdq imm8[1] xmm.uq[0x28001701e286710d,0xd4000b81d7f0f773] xmm.uq[0xaa0005c1c2a63aaa,0x550002e…
3 pclmulqdq imm8[16] xmm.uq[0x2a800171beae2d11,0xd54000b9b604d579] xmm.uq[0xaaa0005db1b029ad,0x955000…
4 pclmulqdq imm8[17] xmm.uq[0x8aa80018be70a8d2,0x4554000d3de61358] xmm.uq[0x22aa00077da0c89b,0xd15500…
5 pclmulqdq imm8[0] m128.uq[0x68aa8003296cd08e,0x3455400273642736] xmm.uq[0x1a2aa002185fd28a,0x0d1550…
6 pclmulqdq imm8[1] m128.uq[0x068aa801d41c9309,0xc3455401c0bc0875] xmm.uq[0xa1a2aa01c70bc327,0x90d155…
7 pclmulqdq imm8[16] m128.uq[0x4868aa81c3c78f2f,0xe4345541c8918684] xmm.uq[0x721a2aa1c2f68231,0xf90d1…
8 pclmulqdq imm8[17] m128.uq[0xbc868aa9cac23ef5,0x9e434555cc0ede67] xmm.uq[0x8f21a2abccb52e20,0x4790d…
9 pclmulqdq imm8[0] xmm.uq[0xe3c868ac4931e9ec,0x71e434570346b3e5] xmm.uq[0xf8f21a2c685118df,0xbc790d1…
10 pclmulqdq imm8[1] xmm.uq[0x5e3c868c6c18e49d,0xef1e43471cba313b] xmm.uq[0xb78f21a4650ad78e,0x5bc790d…
[all …]
H A Dinsn_ssse3.def65 palignr imm8[16] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
66 palignr imm8[23] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
67 palignr imm8[53] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
68 palignr imm8[91] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
69 palignr imm8[137] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
70 palignr imm8[193] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
71 palignr imm8[241] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
72 palignr imm8[255] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
90 palignr imm8[16] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
91 palignr imm8[23] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
[all …]
/dports/devel/valgrind/valgrind-dragonfly-dragonfly/none/tests/amd64/
H A Dinsn_pclmulqdq.def1 pclmulqdq imm8[0] xmm.uq[0x00017004200ab0cd,0xc000b802f6b31753] xmm.uq[0xa0005c0252074a9a,0x50002e0…
2 pclmulqdq imm8[1] xmm.uq[0x28001701e286710d,0xd4000b81d7f0f773] xmm.uq[0xaa0005c1c2a63aaa,0x550002e…
3 pclmulqdq imm8[16] xmm.uq[0x2a800171beae2d11,0xd54000b9b604d579] xmm.uq[0xaaa0005db1b029ad,0x955000…
4 pclmulqdq imm8[17] xmm.uq[0x8aa80018be70a8d2,0x4554000d3de61358] xmm.uq[0x22aa00077da0c89b,0xd15500…
5 pclmulqdq imm8[0] m128.uq[0x68aa8003296cd08e,0x3455400273642736] xmm.uq[0x1a2aa002185fd28a,0x0d1550…
6 pclmulqdq imm8[1] m128.uq[0x068aa801d41c9309,0xc3455401c0bc0875] xmm.uq[0xa1a2aa01c70bc327,0x90d155…
7 pclmulqdq imm8[16] m128.uq[0x4868aa81c3c78f2f,0xe4345541c8918684] xmm.uq[0x721a2aa1c2f68231,0xf90d1…
8 pclmulqdq imm8[17] m128.uq[0xbc868aa9cac23ef5,0x9e434555cc0ede67] xmm.uq[0x8f21a2abccb52e20,0x4790d…
9 pclmulqdq imm8[0] xmm.uq[0xe3c868ac4931e9ec,0x71e434570346b3e5] xmm.uq[0xf8f21a2c685118df,0xbc790d1…
10 pclmulqdq imm8[1] xmm.uq[0x5e3c868c6c18e49d,0xef1e43471cba313b] xmm.uq[0xb78f21a4650ad78e,0x5bc790d…
[all …]
H A Dinsn_ssse3.def65 palignr imm8[16] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
66 palignr imm8[23] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
67 palignr imm8[53] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
68 palignr imm8[91] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
69 palignr imm8[137] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
70 palignr imm8[193] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
71 palignr imm8[241] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
72 palignr imm8[255] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
90 palignr imm8[16] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
91 palignr imm8[23] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
[all …]
/dports/devel/valgrind/valgrind-dragonfly-dragonfly/none/tests/x86/
H A Dinsn_ssse3.def65 palignr imm8[16] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
66 palignr imm8[23] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
67 palignr imm8[53] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
68 palignr imm8[91] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
69 palignr imm8[137] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
70 palignr imm8[193] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
71 palignr imm8[241] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
72 palignr imm8[255] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
90 palignr imm8[16] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
91 palignr imm8[23] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
[all …]
/dports/devel/valgrind-lts/valgrind-dragonfly-dragonfly/none/tests/x86/
H A Dinsn_ssse3.def65 palignr imm8[16] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
66 palignr imm8[23] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
67 palignr imm8[53] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
68 palignr imm8[91] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
69 palignr imm8[137] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
70 palignr imm8[193] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
71 palignr imm8[241] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
72 palignr imm8[255] mm.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
90 palignr imm8[16] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
91 palignr imm8[23] m64.uq[0xFFEEDDCCBBAA9988] mm.uq[0x7766554433221134] => 2.uq[0]
[all …]
/dports/games/libretro-gpsp/gpsp-300d0c0/arm/
H A Darm_dpimacros.h44 #define _MOV_REG_IMM(reg, imm8, rot) \ argument
49 #define _MOVS_REG_IMM(reg, imm8, rot) \ argument
57 #define ARM_MOV_REG_IMM8(p, reg, imm8) \ argument
68 #define _MOV_REG_IMM8(reg, imm8) \ argument
73 #define _MOVS_REG_IMM8(reg, imm8) \ argument
189 #define _MVN_REG_IMM8(reg, imm8) \ argument
194 #define _MVNS_REG_IMM8(reg, imm8) \ argument
1424 #define _TST_REG_IMM8(rn, imm8) \ argument
1480 #define _TEQ_REG_IMM8(rn, imm8) \ argument
1536 #define _CMP_REG_IMM8(rn, imm8) \ argument
[all …]
/dports/lang/mono/mono-5.10.1.57/mono/arch/arm/
H A Darm_dpimacros.h9 #define ARM_MOV_REG_IMM(p, reg, imm8, rot) \ argument
20 #define _MOV_REG_IMM(reg, imm8, rot) \ argument
25 #define _MOVS_REG_IMM(reg, imm8, rot) \ argument
33 #define ARM_MOV_REG_IMM8(p, reg, imm8) \ argument
44 #define _MOV_REG_IMM8(reg, imm8) \ argument
49 #define _MOVS_REG_IMM8(reg, imm8) \ argument
165 #define _MVN_REG_IMM8(reg, imm8) \ argument
170 #define _MVNS_REG_IMM8(reg, imm8) \ argument
1400 #define _TST_REG_IMM8(rn, imm8) \ argument
1456 #define _TEQ_REG_IMM8(rn, imm8) \ argument
[all …]
/dports/emulators/yuzu/yuzu-0b47f7a46/externals/dynarmic/src/frontend/
H A Dimm.cpp13 u64 AdvSIMDExpandImm(bool op, Imm<4> cmode, Imm<8> imm8) { in AdvSIMDExpandImm() argument
16 return Common::Replicate<u64>(imm8.ZeroExtend<u64>(), 32); in AdvSIMDExpandImm()
18 return Common::Replicate<u64>(imm8.ZeroExtend<u64>() << 8, 32); in AdvSIMDExpandImm()
20 return Common::Replicate<u64>(imm8.ZeroExtend<u64>() << 16, 32); in AdvSIMDExpandImm()
24 return Common::Replicate<u64>(imm8.ZeroExtend<u64>(), 16); in AdvSIMDExpandImm()
34 return Common::Replicate<u64>(imm8.ZeroExtend<u64>(), 8); in AdvSIMDExpandImm()
50 result |= imm8.Bit<7>() ? 0x80000000 : 0; in AdvSIMDExpandImm()
51 result |= imm8.Bit<6>() ? 0x3E000000 : 0x40000000; in AdvSIMDExpandImm()
52 result |= imm8.Bits<0, 5, u64>() << 19; in AdvSIMDExpandImm()
57 result |= imm8.Bit<7>() ? 0x80000000'00000000 : 0; in AdvSIMDExpandImm()
[all …]
/dports/emulators/citra-qt5/citra-ac98458e0/externals/dynarmic/src/frontend/
H A Dimm.cpp13 u64 AdvSIMDExpandImm(bool op, Imm<4> cmode, Imm<8> imm8) { in AdvSIMDExpandImm() argument
16 return Common::Replicate<u64>(imm8.ZeroExtend<u64>(), 32); in AdvSIMDExpandImm()
18 return Common::Replicate<u64>(imm8.ZeroExtend<u64>() << 8, 32); in AdvSIMDExpandImm()
20 return Common::Replicate<u64>(imm8.ZeroExtend<u64>() << 16, 32); in AdvSIMDExpandImm()
24 return Common::Replicate<u64>(imm8.ZeroExtend<u64>(), 16); in AdvSIMDExpandImm()
34 return Common::Replicate<u64>(imm8.ZeroExtend<u64>(), 8); in AdvSIMDExpandImm()
50 result |= imm8.Bit<7>() ? 0x80000000 : 0; in AdvSIMDExpandImm()
51 result |= imm8.Bit<6>() ? 0x3E000000 : 0x40000000; in AdvSIMDExpandImm()
52 result |= imm8.Bits<0, 5, u64>() << 19; in AdvSIMDExpandImm()
57 result |= imm8.Bit<7>() ? 0x80000000'00000000 : 0; in AdvSIMDExpandImm()
[all …]

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