| /dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/gallium/drivers/r300/compiler/ |
| H A D | radeon_program_tex.c | 84 struct rc_instruction *inst_mul, *inst_rcp; in projective_divide() local
100 inst_mul->U.I.Opcode = RC_OPCODE_MUL; in projective_divide()
101 inst_mul->U.I.DstReg.File = RC_FILE_TEMPORARY; in projective_divide()
102 inst_mul->U.I.DstReg.Index = temp; in projective_divide()
103 inst_mul->U.I.SrcReg[0] = inst->U.I.SrcReg[0]; in projective_divide()
105 inst_mul->U.I.SrcReg[1].Index = temp; in projective_divide()
192 inst_mul->U.I.DstReg.Index = tmp_sum; in radeonTransformTEX()
196 inst_mul->U.I.SrcReg[0].Swizzle = in radeonTransformTEX()
200 inst_mul->U.I.SrcReg[1].Index = tmp_sum; in radeonTransformTEX()
329 inst_mul->U.I.Opcode = RC_OPCODE_MUL; in radeonTransformTEX()
[all …]
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| H A D | radeon_optimize.c | 724 struct rc_instruction * inst_mul, in peephole_mul_omod() argument
753 if (inst_mul->U.I.SrcReg[i].Negate) { in peephole_mul_omod()
761 GET_SWZ(inst_mul->U.I.SrcReg[i].Swizzle, j); in peephole_mul_omod()
782 inst_mul->U.I.SrcReg[const_index].Index)) { in peephole_mul_omod()
786 inst_mul->U.I.SrcReg[const_index].Index, in peephole_mul_omod()
787 inst_mul->U.I.SrcReg[const_index].Swizzle, in peephole_mul_omod()
788 inst_mul->U.I.SrcReg[const_index].Negate, in peephole_mul_omod()
815 cb_data.Writer = &inst_mul->U.I.DstReg; in peephole_mul_omod()
826 for (inst = inst_mul->Prev; inst != var->Inst; in peephole_mul_omod()
855 inst_mul->U.I.DstReg.WriteMask); in peephole_mul_omod()
[all …]
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| H A D | radeon_compiler.c | 226 struct rc_instruction * inst_mul; in rc_transform_fragment_wpos() local
245 inst_mul = rc_insert_new_instruction(c, inst_rcp); in rc_transform_fragment_wpos()
246 inst_mul->U.I.Opcode = RC_OPCODE_MUL; in rc_transform_fragment_wpos()
248 inst_mul->U.I.DstReg.File = RC_FILE_TEMPORARY; in rc_transform_fragment_wpos()
249 inst_mul->U.I.DstReg.Index = tempregi; in rc_transform_fragment_wpos()
250 inst_mul->U.I.DstReg.WriteMask = RC_MASK_XYZ; in rc_transform_fragment_wpos()
252 inst_mul->U.I.SrcReg[0].File = RC_FILE_INPUT; in rc_transform_fragment_wpos()
253 inst_mul->U.I.SrcReg[0].Index = new_input; in rc_transform_fragment_wpos()
255 inst_mul->U.I.SrcReg[1].File = RC_FILE_TEMPORARY; in rc_transform_fragment_wpos()
256 inst_mul->U.I.SrcReg[1].Index = tempregi; in rc_transform_fragment_wpos()
[all …]
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| /dports/lang/clover/mesa-21.3.6/src/gallium/drivers/r300/compiler/ |
| H A D | radeon_program_tex.c | 84 struct rc_instruction *inst_mul, *inst_rcp; in projective_divide() local
100 inst_mul->U.I.Opcode = RC_OPCODE_MUL; in projective_divide()
101 inst_mul->U.I.DstReg.File = RC_FILE_TEMPORARY; in projective_divide()
102 inst_mul->U.I.DstReg.Index = temp; in projective_divide()
103 inst_mul->U.I.SrcReg[0] = inst->U.I.SrcReg[0]; in projective_divide()
105 inst_mul->U.I.SrcReg[1].Index = temp; in projective_divide()
193 inst_mul->U.I.DstReg.Index = tmp_sum; in radeonTransformTEX()
197 inst_mul->U.I.SrcReg[0].Swizzle = in radeonTransformTEX()
201 inst_mul->U.I.SrcReg[1].Index = tmp_sum; in radeonTransformTEX()
330 inst_mul->U.I.Opcode = RC_OPCODE_MUL; in radeonTransformTEX()
[all …]
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| H A D | radeon_optimize.c | 720 struct rc_instruction * inst_mul, in peephole_mul_omod() argument
749 if (inst_mul->U.I.SrcReg[i].Negate) { in peephole_mul_omod()
757 GET_SWZ(inst_mul->U.I.SrcReg[i].Swizzle, j); in peephole_mul_omod()
778 inst_mul->U.I.SrcReg[const_index].Index)) { in peephole_mul_omod()
782 inst_mul->U.I.SrcReg[const_index].Index, in peephole_mul_omod()
783 inst_mul->U.I.SrcReg[const_index].Swizzle, in peephole_mul_omod()
784 inst_mul->U.I.SrcReg[const_index].Negate, in peephole_mul_omod()
811 cb_data.Writer = &inst_mul->U.I.DstReg; in peephole_mul_omod()
822 for (inst = inst_mul->Prev; inst != var->Inst; in peephole_mul_omod()
851 inst_mul->U.I.DstReg.WriteMask); in peephole_mul_omod()
[all …]
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| H A D | radeon_compiler.c | 242 struct rc_instruction * inst_mul; in rc_transform_fragment_wpos() local
261 inst_mul = rc_insert_new_instruction(c, inst_rcp); in rc_transform_fragment_wpos()
262 inst_mul->U.I.Opcode = RC_OPCODE_MUL; in rc_transform_fragment_wpos()
264 inst_mul->U.I.DstReg.File = RC_FILE_TEMPORARY; in rc_transform_fragment_wpos()
265 inst_mul->U.I.DstReg.Index = tempregi; in rc_transform_fragment_wpos()
266 inst_mul->U.I.DstReg.WriteMask = RC_MASK_XYZ; in rc_transform_fragment_wpos()
268 inst_mul->U.I.SrcReg[0].File = RC_FILE_INPUT; in rc_transform_fragment_wpos()
269 inst_mul->U.I.SrcReg[0].Index = new_input; in rc_transform_fragment_wpos()
271 inst_mul->U.I.SrcReg[1].File = RC_FILE_TEMPORARY; in rc_transform_fragment_wpos()
272 inst_mul->U.I.SrcReg[1].Index = tempregi; in rc_transform_fragment_wpos()
[all …]
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| /dports/graphics/libosmesa/mesa-21.3.6/src/gallium/drivers/r300/compiler/ |
| H A D | radeon_program_tex.c | 84 struct rc_instruction *inst_mul, *inst_rcp; in projective_divide() local
100 inst_mul->U.I.Opcode = RC_OPCODE_MUL; in projective_divide()
101 inst_mul->U.I.DstReg.File = RC_FILE_TEMPORARY; in projective_divide()
102 inst_mul->U.I.DstReg.Index = temp; in projective_divide()
103 inst_mul->U.I.SrcReg[0] = inst->U.I.SrcReg[0]; in projective_divide()
105 inst_mul->U.I.SrcReg[1].Index = temp; in projective_divide()
193 inst_mul->U.I.DstReg.Index = tmp_sum; in radeonTransformTEX()
197 inst_mul->U.I.SrcReg[0].Swizzle = in radeonTransformTEX()
201 inst_mul->U.I.SrcReg[1].Index = tmp_sum; in radeonTransformTEX()
330 inst_mul->U.I.Opcode = RC_OPCODE_MUL; in radeonTransformTEX()
[all …]
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| H A D | radeon_optimize.c | 720 struct rc_instruction * inst_mul, in peephole_mul_omod() argument
749 if (inst_mul->U.I.SrcReg[i].Negate) { in peephole_mul_omod()
757 GET_SWZ(inst_mul->U.I.SrcReg[i].Swizzle, j); in peephole_mul_omod()
778 inst_mul->U.I.SrcReg[const_index].Index)) { in peephole_mul_omod()
782 inst_mul->U.I.SrcReg[const_index].Index, in peephole_mul_omod()
783 inst_mul->U.I.SrcReg[const_index].Swizzle, in peephole_mul_omod()
784 inst_mul->U.I.SrcReg[const_index].Negate, in peephole_mul_omod()
811 cb_data.Writer = &inst_mul->U.I.DstReg; in peephole_mul_omod()
822 for (inst = inst_mul->Prev; inst != var->Inst; in peephole_mul_omod()
851 inst_mul->U.I.DstReg.WriteMask); in peephole_mul_omod()
[all …]
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| H A D | radeon_compiler.c | 242 struct rc_instruction * inst_mul; in rc_transform_fragment_wpos() local
261 inst_mul = rc_insert_new_instruction(c, inst_rcp); in rc_transform_fragment_wpos()
262 inst_mul->U.I.Opcode = RC_OPCODE_MUL; in rc_transform_fragment_wpos()
264 inst_mul->U.I.DstReg.File = RC_FILE_TEMPORARY; in rc_transform_fragment_wpos()
265 inst_mul->U.I.DstReg.Index = tempregi; in rc_transform_fragment_wpos()
266 inst_mul->U.I.DstReg.WriteMask = RC_MASK_XYZ; in rc_transform_fragment_wpos()
268 inst_mul->U.I.SrcReg[0].File = RC_FILE_INPUT; in rc_transform_fragment_wpos()
269 inst_mul->U.I.SrcReg[0].Index = new_input; in rc_transform_fragment_wpos()
271 inst_mul->U.I.SrcReg[1].File = RC_FILE_TEMPORARY; in rc_transform_fragment_wpos()
272 inst_mul->U.I.SrcReg[1].Index = tempregi; in rc_transform_fragment_wpos()
[all …]
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| /dports/graphics/libosmesa-gallium/mesa-21.3.6/src/gallium/drivers/r300/compiler/ |
| H A D | radeon_program_tex.c | 84 struct rc_instruction *inst_mul, *inst_rcp; in projective_divide() local
100 inst_mul->U.I.Opcode = RC_OPCODE_MUL; in projective_divide()
101 inst_mul->U.I.DstReg.File = RC_FILE_TEMPORARY; in projective_divide()
102 inst_mul->U.I.DstReg.Index = temp; in projective_divide()
103 inst_mul->U.I.SrcReg[0] = inst->U.I.SrcReg[0]; in projective_divide()
105 inst_mul->U.I.SrcReg[1].Index = temp; in projective_divide()
193 inst_mul->U.I.DstReg.Index = tmp_sum; in radeonTransformTEX()
197 inst_mul->U.I.SrcReg[0].Swizzle = in radeonTransformTEX()
201 inst_mul->U.I.SrcReg[1].Index = tmp_sum; in radeonTransformTEX()
330 inst_mul->U.I.Opcode = RC_OPCODE_MUL; in radeonTransformTEX()
[all …]
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| H A D | radeon_optimize.c | 720 struct rc_instruction * inst_mul, in peephole_mul_omod() argument
749 if (inst_mul->U.I.SrcReg[i].Negate) { in peephole_mul_omod()
757 GET_SWZ(inst_mul->U.I.SrcReg[i].Swizzle, j); in peephole_mul_omod()
778 inst_mul->U.I.SrcReg[const_index].Index)) { in peephole_mul_omod()
782 inst_mul->U.I.SrcReg[const_index].Index, in peephole_mul_omod()
783 inst_mul->U.I.SrcReg[const_index].Swizzle, in peephole_mul_omod()
784 inst_mul->U.I.SrcReg[const_index].Negate, in peephole_mul_omod()
811 cb_data.Writer = &inst_mul->U.I.DstReg; in peephole_mul_omod()
822 for (inst = inst_mul->Prev; inst != var->Inst; in peephole_mul_omod()
851 inst_mul->U.I.DstReg.WriteMask); in peephole_mul_omod()
[all …]
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| /dports/graphics/mesa-libs/mesa-21.3.6/src/gallium/drivers/r300/compiler/ |
| H A D | radeon_program_tex.c | 84 struct rc_instruction *inst_mul, *inst_rcp; in projective_divide() local
100 inst_mul->U.I.Opcode = RC_OPCODE_MUL; in projective_divide()
101 inst_mul->U.I.DstReg.File = RC_FILE_TEMPORARY; in projective_divide()
102 inst_mul->U.I.DstReg.Index = temp; in projective_divide()
103 inst_mul->U.I.SrcReg[0] = inst->U.I.SrcReg[0]; in projective_divide()
105 inst_mul->U.I.SrcReg[1].Index = temp; in projective_divide()
193 inst_mul->U.I.DstReg.Index = tmp_sum; in radeonTransformTEX()
197 inst_mul->U.I.SrcReg[0].Swizzle = in radeonTransformTEX()
201 inst_mul->U.I.SrcReg[1].Index = tmp_sum; in radeonTransformTEX()
330 inst_mul->U.I.Opcode = RC_OPCODE_MUL; in radeonTransformTEX()
[all …]
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| H A D | radeon_optimize.c | 720 struct rc_instruction * inst_mul, in peephole_mul_omod() argument
749 if (inst_mul->U.I.SrcReg[i].Negate) { in peephole_mul_omod()
757 GET_SWZ(inst_mul->U.I.SrcReg[i].Swizzle, j); in peephole_mul_omod()
778 inst_mul->U.I.SrcReg[const_index].Index)) { in peephole_mul_omod()
782 inst_mul->U.I.SrcReg[const_index].Index, in peephole_mul_omod()
783 inst_mul->U.I.SrcReg[const_index].Swizzle, in peephole_mul_omod()
784 inst_mul->U.I.SrcReg[const_index].Negate, in peephole_mul_omod()
811 cb_data.Writer = &inst_mul->U.I.DstReg; in peephole_mul_omod()
822 for (inst = inst_mul->Prev; inst != var->Inst; in peephole_mul_omod()
851 inst_mul->U.I.DstReg.WriteMask); in peephole_mul_omod()
[all …]
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| /dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/gallium/drivers/r300/compiler/ |
| H A D | radeon_program_tex.c | 84 struct rc_instruction *inst_mul, *inst_rcp; in projective_divide() local
100 inst_mul->U.I.Opcode = RC_OPCODE_MUL; in projective_divide()
101 inst_mul->U.I.DstReg.File = RC_FILE_TEMPORARY; in projective_divide()
102 inst_mul->U.I.DstReg.Index = temp; in projective_divide()
103 inst_mul->U.I.SrcReg[0] = inst->U.I.SrcReg[0]; in projective_divide()
105 inst_mul->U.I.SrcReg[1].Index = temp; in projective_divide()
193 inst_mul->U.I.DstReg.Index = tmp_sum; in radeonTransformTEX()
197 inst_mul->U.I.SrcReg[0].Swizzle = in radeonTransformTEX()
201 inst_mul->U.I.SrcReg[1].Index = tmp_sum; in radeonTransformTEX()
330 inst_mul->U.I.Opcode = RC_OPCODE_MUL; in radeonTransformTEX()
[all …]
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| H A D | radeon_optimize.c | 720 struct rc_instruction * inst_mul, in peephole_mul_omod() argument
749 if (inst_mul->U.I.SrcReg[i].Negate) { in peephole_mul_omod()
757 GET_SWZ(inst_mul->U.I.SrcReg[i].Swizzle, j); in peephole_mul_omod()
778 inst_mul->U.I.SrcReg[const_index].Index)) { in peephole_mul_omod()
782 inst_mul->U.I.SrcReg[const_index].Index, in peephole_mul_omod()
783 inst_mul->U.I.SrcReg[const_index].Swizzle, in peephole_mul_omod()
784 inst_mul->U.I.SrcReg[const_index].Negate, in peephole_mul_omod()
811 cb_data.Writer = &inst_mul->U.I.DstReg; in peephole_mul_omod()
822 for (inst = inst_mul->Prev; inst != var->Inst; in peephole_mul_omod()
851 inst_mul->U.I.DstReg.WriteMask); in peephole_mul_omod()
[all …]
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| /dports/graphics/mesa-dri-classic/mesa-20.2.3/src/gallium/drivers/r300/compiler/ |
| H A D | radeon_program_tex.c | 84 struct rc_instruction *inst_mul, *inst_rcp; in projective_divide() local
100 inst_mul->U.I.Opcode = RC_OPCODE_MUL; in projective_divide()
101 inst_mul->U.I.DstReg.File = RC_FILE_TEMPORARY; in projective_divide()
102 inst_mul->U.I.DstReg.Index = temp; in projective_divide()
103 inst_mul->U.I.SrcReg[0] = inst->U.I.SrcReg[0]; in projective_divide()
105 inst_mul->U.I.SrcReg[1].Index = temp; in projective_divide()
193 inst_mul->U.I.DstReg.Index = tmp_sum; in radeonTransformTEX()
197 inst_mul->U.I.SrcReg[0].Swizzle = in radeonTransformTEX()
201 inst_mul->U.I.SrcReg[1].Index = tmp_sum; in radeonTransformTEX()
330 inst_mul->U.I.Opcode = RC_OPCODE_MUL; in radeonTransformTEX()
[all …]
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| H A D | radeon_optimize.c | 717 struct rc_instruction * inst_mul, in peephole_mul_omod() argument
746 if (inst_mul->U.I.SrcReg[i].Negate) { in peephole_mul_omod()
754 GET_SWZ(inst_mul->U.I.SrcReg[i].Swizzle, j); in peephole_mul_omod()
775 inst_mul->U.I.SrcReg[const_index].Index)) { in peephole_mul_omod()
779 inst_mul->U.I.SrcReg[const_index].Index, in peephole_mul_omod()
780 inst_mul->U.I.SrcReg[const_index].Swizzle, in peephole_mul_omod()
781 inst_mul->U.I.SrcReg[const_index].Negate, in peephole_mul_omod()
808 cb_data.Writer = &inst_mul->U.I.DstReg; in peephole_mul_omod()
819 for (inst = inst_mul->Prev; inst != var->Inst; in peephole_mul_omod()
841 inst_mul->U.I.DstReg.WriteMask); in peephole_mul_omod()
[all …]
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| /dports/graphics/mesa-gallium-va/mesa-21.3.6/src/gallium/drivers/r300/compiler/ |
| H A D | radeon_program_tex.c | 84 struct rc_instruction *inst_mul, *inst_rcp; in projective_divide() local
100 inst_mul->U.I.Opcode = RC_OPCODE_MUL; in projective_divide()
101 inst_mul->U.I.DstReg.File = RC_FILE_TEMPORARY; in projective_divide()
102 inst_mul->U.I.DstReg.Index = temp; in projective_divide()
103 inst_mul->U.I.SrcReg[0] = inst->U.I.SrcReg[0]; in projective_divide()
105 inst_mul->U.I.SrcReg[1].Index = temp; in projective_divide()
193 inst_mul->U.I.DstReg.Index = tmp_sum; in radeonTransformTEX()
197 inst_mul->U.I.SrcReg[0].Swizzle = in radeonTransformTEX()
201 inst_mul->U.I.SrcReg[1].Index = tmp_sum; in radeonTransformTEX()
330 inst_mul->U.I.Opcode = RC_OPCODE_MUL; in radeonTransformTEX()
[all …]
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| H A D | radeon_optimize.c | 720 struct rc_instruction * inst_mul, in peephole_mul_omod() argument
749 if (inst_mul->U.I.SrcReg[i].Negate) { in peephole_mul_omod()
757 GET_SWZ(inst_mul->U.I.SrcReg[i].Swizzle, j); in peephole_mul_omod()
778 inst_mul->U.I.SrcReg[const_index].Index)) { in peephole_mul_omod()
782 inst_mul->U.I.SrcReg[const_index].Index, in peephole_mul_omod()
783 inst_mul->U.I.SrcReg[const_index].Swizzle, in peephole_mul_omod()
784 inst_mul->U.I.SrcReg[const_index].Negate, in peephole_mul_omod()
811 cb_data.Writer = &inst_mul->U.I.DstReg; in peephole_mul_omod()
822 for (inst = inst_mul->Prev; inst != var->Inst; in peephole_mul_omod()
851 inst_mul->U.I.DstReg.WriteMask); in peephole_mul_omod()
[all …]
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| /dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/gallium/drivers/r300/compiler/ |
| H A D | radeon_program_tex.c | 84 struct rc_instruction *inst_mul, *inst_rcp; in projective_divide() local
100 inst_mul->U.I.Opcode = RC_OPCODE_MUL; in projective_divide()
101 inst_mul->U.I.DstReg.File = RC_FILE_TEMPORARY; in projective_divide()
102 inst_mul->U.I.DstReg.Index = temp; in projective_divide()
103 inst_mul->U.I.SrcReg[0] = inst->U.I.SrcReg[0]; in projective_divide()
105 inst_mul->U.I.SrcReg[1].Index = temp; in projective_divide()
193 inst_mul->U.I.DstReg.Index = tmp_sum; in radeonTransformTEX()
197 inst_mul->U.I.SrcReg[0].Swizzle = in radeonTransformTEX()
201 inst_mul->U.I.SrcReg[1].Index = tmp_sum; in radeonTransformTEX()
330 inst_mul->U.I.Opcode = RC_OPCODE_MUL; in radeonTransformTEX()
[all …]
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| H A D | radeon_optimize.c | 720 struct rc_instruction * inst_mul, in peephole_mul_omod() argument
749 if (inst_mul->U.I.SrcReg[i].Negate) { in peephole_mul_omod()
757 GET_SWZ(inst_mul->U.I.SrcReg[i].Swizzle, j); in peephole_mul_omod()
778 inst_mul->U.I.SrcReg[const_index].Index)) { in peephole_mul_omod()
782 inst_mul->U.I.SrcReg[const_index].Index, in peephole_mul_omod()
783 inst_mul->U.I.SrcReg[const_index].Swizzle, in peephole_mul_omod()
784 inst_mul->U.I.SrcReg[const_index].Negate, in peephole_mul_omod()
811 cb_data.Writer = &inst_mul->U.I.DstReg; in peephole_mul_omod()
822 for (inst = inst_mul->Prev; inst != var->Inst; in peephole_mul_omod()
851 inst_mul->U.I.DstReg.WriteMask); in peephole_mul_omod()
[all …]
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| /dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/gallium/drivers/r300/compiler/ |
| H A D | radeon_program_tex.c | 84 struct rc_instruction *inst_mul, *inst_rcp; in projective_divide() local
100 inst_mul->U.I.Opcode = RC_OPCODE_MUL; in projective_divide()
101 inst_mul->U.I.DstReg.File = RC_FILE_TEMPORARY; in projective_divide()
102 inst_mul->U.I.DstReg.Index = temp; in projective_divide()
103 inst_mul->U.I.SrcReg[0] = inst->U.I.SrcReg[0]; in projective_divide()
105 inst_mul->U.I.SrcReg[1].Index = temp; in projective_divide()
193 inst_mul->U.I.DstReg.Index = tmp_sum; in radeonTransformTEX()
197 inst_mul->U.I.SrcReg[0].Swizzle = in radeonTransformTEX()
201 inst_mul->U.I.SrcReg[1].Index = tmp_sum; in radeonTransformTEX()
330 inst_mul->U.I.Opcode = RC_OPCODE_MUL; in radeonTransformTEX()
[all …]
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| H A D | radeon_optimize.c | 720 struct rc_instruction * inst_mul, in peephole_mul_omod() argument
749 if (inst_mul->U.I.SrcReg[i].Negate) { in peephole_mul_omod()
757 GET_SWZ(inst_mul->U.I.SrcReg[i].Swizzle, j); in peephole_mul_omod()
778 inst_mul->U.I.SrcReg[const_index].Index)) { in peephole_mul_omod()
782 inst_mul->U.I.SrcReg[const_index].Index, in peephole_mul_omod()
783 inst_mul->U.I.SrcReg[const_index].Swizzle, in peephole_mul_omod()
784 inst_mul->U.I.SrcReg[const_index].Negate, in peephole_mul_omod()
811 cb_data.Writer = &inst_mul->U.I.DstReg; in peephole_mul_omod()
822 for (inst = inst_mul->Prev; inst != var->Inst; in peephole_mul_omod()
851 inst_mul->U.I.DstReg.WriteMask); in peephole_mul_omod()
[all …]
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| /dports/graphics/mesa-dri/mesa-21.3.6/src/gallium/drivers/r300/compiler/ |
| H A D | radeon_program_tex.c | 84 struct rc_instruction *inst_mul, *inst_rcp; in projective_divide() local
100 inst_mul->U.I.Opcode = RC_OPCODE_MUL; in projective_divide()
101 inst_mul->U.I.DstReg.File = RC_FILE_TEMPORARY; in projective_divide()
102 inst_mul->U.I.DstReg.Index = temp; in projective_divide()
103 inst_mul->U.I.SrcReg[0] = inst->U.I.SrcReg[0]; in projective_divide()
105 inst_mul->U.I.SrcReg[1].Index = temp; in projective_divide()
193 inst_mul->U.I.DstReg.Index = tmp_sum; in radeonTransformTEX()
197 inst_mul->U.I.SrcReg[0].Swizzle = in radeonTransformTEX()
201 inst_mul->U.I.SrcReg[1].Index = tmp_sum; in radeonTransformTEX()
330 inst_mul->U.I.Opcode = RC_OPCODE_MUL; in radeonTransformTEX()
[all …]
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| H A D | radeon_optimize.c | 720 struct rc_instruction * inst_mul, in peephole_mul_omod() argument
749 if (inst_mul->U.I.SrcReg[i].Negate) { in peephole_mul_omod()
757 GET_SWZ(inst_mul->U.I.SrcReg[i].Swizzle, j); in peephole_mul_omod()
778 inst_mul->U.I.SrcReg[const_index].Index)) { in peephole_mul_omod()
782 inst_mul->U.I.SrcReg[const_index].Index, in peephole_mul_omod()
783 inst_mul->U.I.SrcReg[const_index].Swizzle, in peephole_mul_omod()
784 inst_mul->U.I.SrcReg[const_index].Negate, in peephole_mul_omod()
811 cb_data.Writer = &inst_mul->U.I.DstReg; in peephole_mul_omod()
822 for (inst = inst_mul->Prev; inst != var->Inst; in peephole_mul_omod()
851 inst_mul->U.I.DstReg.WriteMask); in peephole_mul_omod()
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