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Searched refs:int_status (Results 1 – 25 of 1476) sorted by relevance

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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_dma.c196 if (int_status & SXGBE_DMA_INT_STATUS_TI) { in sxgbe_tx_dma_int_status()
202 if (int_status & SXGBE_DMA_INT_STATUS_TBU) { in sxgbe_tx_dma_int_status()
209 if (int_status & SXGBE_DMA_INT_STATUS_TPS) { in sxgbe_tx_dma_int_status()
215 if (int_status & SXGBE_DMA_INT_STATUS_FBE) { in sxgbe_tx_dma_int_status()
225 if (int_status & SXGBE_DMA_INT_STATUS_TEB0) { in sxgbe_tx_dma_int_status()
232 if (int_status & SXGBE_DMA_INT_STATUS_TEB1) { in sxgbe_tx_dma_int_status()
239 if (int_status & SXGBE_DMA_INT_STATUS_TEB2) { in sxgbe_tx_dma_int_status()
268 if (int_status & SXGBE_DMA_INT_STATUS_RI) { in sxgbe_rx_dma_int_status()
275 if (int_status & SXGBE_DMA_INT_STATUS_RBU) { in sxgbe_rx_dma_int_status()
281 if (int_status & SXGBE_DMA_INT_STATUS_RPS) { in sxgbe_rx_dma_int_status()
[all …]
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_dma.c196 if (int_status & SXGBE_DMA_INT_STATUS_TI) { in sxgbe_tx_dma_int_status()
202 if (int_status & SXGBE_DMA_INT_STATUS_TBU) { in sxgbe_tx_dma_int_status()
209 if (int_status & SXGBE_DMA_INT_STATUS_TPS) { in sxgbe_tx_dma_int_status()
215 if (int_status & SXGBE_DMA_INT_STATUS_FBE) { in sxgbe_tx_dma_int_status()
225 if (int_status & SXGBE_DMA_INT_STATUS_TEB0) { in sxgbe_tx_dma_int_status()
232 if (int_status & SXGBE_DMA_INT_STATUS_TEB1) { in sxgbe_tx_dma_int_status()
239 if (int_status & SXGBE_DMA_INT_STATUS_TEB2) { in sxgbe_tx_dma_int_status()
268 if (int_status & SXGBE_DMA_INT_STATUS_RI) { in sxgbe_rx_dma_int_status()
275 if (int_status & SXGBE_DMA_INT_STATUS_RBU) { in sxgbe_rx_dma_int_status()
281 if (int_status & SXGBE_DMA_INT_STATUS_RPS) { in sxgbe_rx_dma_int_status()
[all …]
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_dma.c196 if (int_status & SXGBE_DMA_INT_STATUS_TI) { in sxgbe_tx_dma_int_status()
202 if (int_status & SXGBE_DMA_INT_STATUS_TBU) { in sxgbe_tx_dma_int_status()
209 if (int_status & SXGBE_DMA_INT_STATUS_TPS) { in sxgbe_tx_dma_int_status()
215 if (int_status & SXGBE_DMA_INT_STATUS_FBE) { in sxgbe_tx_dma_int_status()
225 if (int_status & SXGBE_DMA_INT_STATUS_TEB0) { in sxgbe_tx_dma_int_status()
232 if (int_status & SXGBE_DMA_INT_STATUS_TEB1) { in sxgbe_tx_dma_int_status()
239 if (int_status & SXGBE_DMA_INT_STATUS_TEB2) { in sxgbe_tx_dma_int_status()
268 if (int_status & SXGBE_DMA_INT_STATUS_RI) { in sxgbe_rx_dma_int_status()
275 if (int_status & SXGBE_DMA_INT_STATUS_RBU) { in sxgbe_rx_dma_int_status()
281 if (int_status & SXGBE_DMA_INT_STATUS_RPS) { in sxgbe_rx_dma_int_status()
[all …]
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/i2c/
H A Dzynq_i2c.c96 int int_status; in zynq_i2c_debug_status() local
101 if (int_status || status) { in zynq_i2c_debug_status()
103 if (int_status & ZYNQ_I2C_INTERRUPT_COMP) in zynq_i2c_debug_status()
105 if (int_status & ZYNQ_I2C_INTERRUPT_DATA) in zynq_i2c_debug_status()
107 if (int_status & ZYNQ_I2C_INTERRUPT_NACK) in zynq_i2c_debug_status()
109 if (int_status & ZYNQ_I2C_INTERRUPT_TO) in zynq_i2c_debug_status()
113 if (int_status & ZYNQ_I2C_INTERRUPT_RXOVF) in zynq_i2c_debug_status()
115 if (int_status & ZYNQ_I2C_INTERRUPT_TXOVF) in zynq_i2c_debug_status()
138 int timeout, int_status; in zynq_i2c_wait() local
143 if (int_status & mask) in zynq_i2c_wait()
[all …]
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/i2c/
H A Dzynq_i2c.c96 int int_status; in zynq_i2c_debug_status() local
101 if (int_status || status) { in zynq_i2c_debug_status()
103 if (int_status & ZYNQ_I2C_INTERRUPT_COMP) in zynq_i2c_debug_status()
105 if (int_status & ZYNQ_I2C_INTERRUPT_DATA) in zynq_i2c_debug_status()
107 if (int_status & ZYNQ_I2C_INTERRUPT_NACK) in zynq_i2c_debug_status()
109 if (int_status & ZYNQ_I2C_INTERRUPT_TO) in zynq_i2c_debug_status()
113 if (int_status & ZYNQ_I2C_INTERRUPT_RXOVF) in zynq_i2c_debug_status()
115 if (int_status & ZYNQ_I2C_INTERRUPT_TXOVF) in zynq_i2c_debug_status()
138 int timeout, int_status; in zynq_i2c_wait() local
143 if (int_status & mask) in zynq_i2c_wait()
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/i2c/
H A Dzynq_i2c.c96 int int_status; in zynq_i2c_debug_status() local
101 if (int_status || status) { in zynq_i2c_debug_status()
103 if (int_status & ZYNQ_I2C_INTERRUPT_COMP) in zynq_i2c_debug_status()
105 if (int_status & ZYNQ_I2C_INTERRUPT_DATA) in zynq_i2c_debug_status()
107 if (int_status & ZYNQ_I2C_INTERRUPT_NACK) in zynq_i2c_debug_status()
109 if (int_status & ZYNQ_I2C_INTERRUPT_TO) in zynq_i2c_debug_status()
113 if (int_status & ZYNQ_I2C_INTERRUPT_RXOVF) in zynq_i2c_debug_status()
115 if (int_status & ZYNQ_I2C_INTERRUPT_TXOVF) in zynq_i2c_debug_status()
138 int timeout, int_status; in zynq_i2c_wait() local
143 if (int_status & mask) in zynq_i2c_wait()
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/i2c/
H A Dzynq_i2c.c96 int int_status; in zynq_i2c_debug_status() local
101 if (int_status || status) { in zynq_i2c_debug_status()
103 if (int_status & ZYNQ_I2C_INTERRUPT_COMP) in zynq_i2c_debug_status()
105 if (int_status & ZYNQ_I2C_INTERRUPT_DATA) in zynq_i2c_debug_status()
107 if (int_status & ZYNQ_I2C_INTERRUPT_NACK) in zynq_i2c_debug_status()
109 if (int_status & ZYNQ_I2C_INTERRUPT_TO) in zynq_i2c_debug_status()
113 if (int_status & ZYNQ_I2C_INTERRUPT_RXOVF) in zynq_i2c_debug_status()
115 if (int_status & ZYNQ_I2C_INTERRUPT_TXOVF) in zynq_i2c_debug_status()
138 int timeout, int_status; in zynq_i2c_wait() local
143 if (int_status & mask) in zynq_i2c_wait()
[all …]
/dports/sysutils/u-boot-utilite/u-boot-2015.07/drivers/i2c/
H A Dzynq_i2c.c94 int int_status; in zynq_i2c_debug_status() local
99 if (int_status || status) { in zynq_i2c_debug_status()
101 if (int_status & ZYNQ_I2C_INTERRUPT_COMP) in zynq_i2c_debug_status()
103 if (int_status & ZYNQ_I2C_INTERRUPT_DATA) in zynq_i2c_debug_status()
105 if (int_status & ZYNQ_I2C_INTERRUPT_NACK) in zynq_i2c_debug_status()
107 if (int_status & ZYNQ_I2C_INTERRUPT_TO) in zynq_i2c_debug_status()
111 if (int_status & ZYNQ_I2C_INTERRUPT_RXOVF) in zynq_i2c_debug_status()
113 if (int_status & ZYNQ_I2C_INTERRUPT_TXOVF) in zynq_i2c_debug_status()
136 int timeout, int_status; in zynq_i2c_wait() local
141 if (int_status & mask) in zynq_i2c_wait()
[all …]
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/drivers/i2c/
H A Dzynq_i2c.c96 int int_status; in zynq_i2c_debug_status() local
101 if (int_status || status) { in zynq_i2c_debug_status()
103 if (int_status & ZYNQ_I2C_INTERRUPT_COMP) in zynq_i2c_debug_status()
105 if (int_status & ZYNQ_I2C_INTERRUPT_DATA) in zynq_i2c_debug_status()
107 if (int_status & ZYNQ_I2C_INTERRUPT_NACK) in zynq_i2c_debug_status()
109 if (int_status & ZYNQ_I2C_INTERRUPT_TO) in zynq_i2c_debug_status()
113 if (int_status & ZYNQ_I2C_INTERRUPT_RXOVF) in zynq_i2c_debug_status()
115 if (int_status & ZYNQ_I2C_INTERRUPT_TXOVF) in zynq_i2c_debug_status()
138 int timeout, int_status; in zynq_i2c_wait() local
143 if (int_status & mask) in zynq_i2c_wait()
[all …]
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/board/gdsys/common/
H A Dmclink.c63 u16 int_status; in mclink_send() local
68 FPGA_GET_REG(0, mc_int, &int_status); in mclink_send()
69 FPGA_SET_REG(0, mc_int, int_status); in mclink_send()
78 FPGA_GET_REG(0, mc_int, &int_status); in mclink_send()
79 while (!(int_status & MCINT_RX_PACKET_RECEIVED_EV)) { in mclink_send()
83 FPGA_GET_REG(0, mc_int, &int_status); in mclink_send()
99 u16 int_status; in mclink_receive() local
110 FPGA_GET_REG(0, mc_int, &int_status); in mclink_receive()
111 while (!(int_status & MCINT_RX_CONTENT_AVAILABLE)) { in mclink_receive()
115 FPGA_GET_REG(0, mc_int, &int_status); in mclink_receive()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/board/gdsys/common/
H A Dmclink.c63 u16 int_status; in mclink_send() local
68 FPGA_GET_REG(0, mc_int, &int_status); in mclink_send()
69 FPGA_SET_REG(0, mc_int, int_status); in mclink_send()
78 FPGA_GET_REG(0, mc_int, &int_status); in mclink_send()
79 while (!(int_status & MCINT_RX_PACKET_RECEIVED_EV)) { in mclink_send()
83 FPGA_GET_REG(0, mc_int, &int_status); in mclink_send()
99 u16 int_status; in mclink_receive() local
110 FPGA_GET_REG(0, mc_int, &int_status); in mclink_receive()
111 while (!(int_status & MCINT_RX_CONTENT_AVAILABLE)) { in mclink_receive()
115 FPGA_GET_REG(0, mc_int, &int_status); in mclink_receive()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/board/gdsys/common/
H A Dmclink.c63 u16 int_status; in mclink_send() local
68 FPGA_GET_REG(0, mc_int, &int_status); in mclink_send()
69 FPGA_SET_REG(0, mc_int, int_status); in mclink_send()
78 FPGA_GET_REG(0, mc_int, &int_status); in mclink_send()
79 while (!(int_status & MCINT_RX_PACKET_RECEIVED_EV)) { in mclink_send()
83 FPGA_GET_REG(0, mc_int, &int_status); in mclink_send()
99 u16 int_status; in mclink_receive() local
110 FPGA_GET_REG(0, mc_int, &int_status); in mclink_receive()
111 while (!(int_status & MCINT_RX_CONTENT_AVAILABLE)) { in mclink_receive()
115 FPGA_GET_REG(0, mc_int, &int_status); in mclink_receive()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/board/gdsys/common/
H A Dmclink.c63 u16 int_status; in mclink_send() local
68 FPGA_GET_REG(0, mc_int, &int_status); in mclink_send()
69 FPGA_SET_REG(0, mc_int, int_status); in mclink_send()
78 FPGA_GET_REG(0, mc_int, &int_status); in mclink_send()
79 while (!(int_status & MCINT_RX_PACKET_RECEIVED_EV)) { in mclink_send()
83 FPGA_GET_REG(0, mc_int, &int_status); in mclink_send()
99 u16 int_status; in mclink_receive() local
110 FPGA_GET_REG(0, mc_int, &int_status); in mclink_receive()
111 while (!(int_status & MCINT_RX_CONTENT_AVAILABLE)) { in mclink_receive()
115 FPGA_GET_REG(0, mc_int, &int_status); in mclink_receive()
/dports/sysutils/u-boot-tools/u-boot-2020.07/board/gdsys/common/
H A Dmclink.c66 u16 int_status; in mclink_send() local
71 FPGA_GET_REG(0, mc_int, &int_status); in mclink_send()
72 FPGA_SET_REG(0, mc_int, int_status); in mclink_send()
81 FPGA_GET_REG(0, mc_int, &int_status); in mclink_send()
82 while (!(int_status & MCINT_RX_PACKET_RECEIVED_EV)) { in mclink_send()
86 FPGA_GET_REG(0, mc_int, &int_status); in mclink_send()
102 u16 int_status; in mclink_receive() local
113 FPGA_GET_REG(0, mc_int, &int_status); in mclink_receive()
114 while (!(int_status & MCINT_RX_CONTENT_AVAILABLE)) { in mclink_receive()
118 FPGA_GET_REG(0, mc_int, &int_status); in mclink_receive()
/dports/sysutils/u-boot-utilite/u-boot-2015.07/board/gdsys/common/
H A Dmclink.c64 u16 int_status; in mclink_send() local
69 FPGA_GET_REG(0, mc_int, &int_status); in mclink_send()
70 FPGA_SET_REG(0, mc_int, int_status); in mclink_send()
79 FPGA_GET_REG(0, mc_int, &int_status); in mclink_send()
80 while (!(int_status & MCINT_RX_PACKET_RECEIVED_EV)) { in mclink_send()
84 FPGA_GET_REG(0, mc_int, &int_status); in mclink_send()
100 u16 int_status; in mclink_receive() local
111 FPGA_GET_REG(0, mc_int, &int_status); in mclink_receive()
112 while (!(int_status & MCINT_RX_CONTENT_AVAILABLE)) { in mclink_receive()
116 FPGA_GET_REG(0, mc_int, &int_status); in mclink_receive()
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/board/gdsys/common/
H A Dmclink.c63 u16 int_status; in mclink_send() local
68 FPGA_GET_REG(0, mc_int, &int_status); in mclink_send()
69 FPGA_SET_REG(0, mc_int, int_status); in mclink_send()
78 FPGA_GET_REG(0, mc_int, &int_status); in mclink_send()
79 while (!(int_status & MCINT_RX_PACKET_RECEIVED_EV)) { in mclink_send()
83 FPGA_GET_REG(0, mc_int, &int_status); in mclink_send()
99 u16 int_status; in mclink_receive() local
110 FPGA_GET_REG(0, mc_int, &int_status); in mclink_receive()
111 while (!(int_status & MCINT_RX_CONTENT_AVAILABLE)) { in mclink_receive()
115 FPGA_GET_REG(0, mc_int, &int_status); in mclink_receive()
/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/mips/loongson2ef/common/
H A Dirq.c15 u32 int_status; in bonito_irqdispatch() local
19 int_status = LOONGSON_INTISR; in bonito_irqdispatch()
20 while (int_status & (1 << 10)) { in bonito_irqdispatch()
22 int_status = LOONGSON_INTISR; in bonito_irqdispatch()
26 int_status = LOONGSON_INTISR & LOONGSON_INTEN; in bonito_irqdispatch()
28 if (int_status) { in bonito_irqdispatch()
29 i = __ffs(int_status); in bonito_irqdispatch()
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/mips/loongson2ef/common/
H A Dirq.c15 u32 int_status; in bonito_irqdispatch() local
19 int_status = LOONGSON_INTISR; in bonito_irqdispatch()
20 while (int_status & (1 << 10)) { in bonito_irqdispatch()
22 int_status = LOONGSON_INTISR; in bonito_irqdispatch()
26 int_status = LOONGSON_INTISR & LOONGSON_INTEN; in bonito_irqdispatch()
28 if (int_status) { in bonito_irqdispatch()
29 i = __ffs(int_status); in bonito_irqdispatch()
/dports/multimedia/libv4l/linux-5.13-rc2/arch/mips/loongson2ef/common/
H A Dirq.c15 u32 int_status; in bonito_irqdispatch() local
19 int_status = LOONGSON_INTISR; in bonito_irqdispatch()
20 while (int_status & (1 << 10)) { in bonito_irqdispatch()
22 int_status = LOONGSON_INTISR; in bonito_irqdispatch()
26 int_status = LOONGSON_INTISR & LOONGSON_INTEN; in bonito_irqdispatch()
28 if (int_status) { in bonito_irqdispatch()
29 i = __ffs(int_status); in bonito_irqdispatch()
/dports/emulators/gxemul/gxemul-0.6.3/src/devices/
H A Ddev_bebox.cc75 uint32_t int_status; member
84 d->int_status |= interrupt->line; in bebox_interrupt_assert()
89 if (d->int_status & d->cpu0_int_mask) in bebox_interrupt_assert()
91 if (d->int_status & d->cpu1_int_mask) in bebox_interrupt_assert()
97 d->int_status &= ~interrupt->line; in bebox_interrupt_deassert()
99 if (!(d->int_status & d->cpu0_int_mask)) in bebox_interrupt_deassert()
101 if (!(d->int_status & d->cpu1_int_mask)) in bebox_interrupt_deassert()
158 odata = d->int_status; in DEVICE_ACCESS()
161 d->int_status |= idata; in DEVICE_ACCESS()
163 d->int_status &= ~idata; in DEVICE_ACCESS()
[all …]
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/post/cpu/ppc4xx/
H A Ddenali_ecc.c94 uint32_t int_status; in get_ecc_status() local
101 mfsdram(DDR0_00, int_status); in get_ecc_status()
102 int_status &= DDR0_00_INT_STATUS_MASK; in get_ecc_status()
105 if (int_status & (DDR0_00_INT_STATUS_BIT0 | DDR0_00_INT_STATUS_BIT1)) { in get_ecc_status()
109 if (int_status & DDR0_00_INT_STATUS_BIT1) in get_ecc_status()
117 if (int_status & (DDR0_00_INT_STATUS_BIT2 | DDR0_00_INT_STATUS_BIT3)) { in get_ecc_status()
131 if (int_status & DDR0_00_INT_STATUS_BIT3) in get_ecc_status()
139 if (int_status & (DDR0_00_INT_STATUS_BIT4 | DDR0_00_INT_STATUS_BIT5)) { in get_ecc_status()
147 if (int_status & DDR0_00_INT_STATUS_BIT5) in get_ecc_status()
156 if (int_status & DDR0_00_INT_STATUS_BIT6) in get_ecc_status()
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/post/cpu/ppc4xx/
H A Ddenali_ecc.c94 uint32_t int_status; in get_ecc_status() local
101 mfsdram(DDR0_00, int_status); in get_ecc_status()
102 int_status &= DDR0_00_INT_STATUS_MASK; in get_ecc_status()
105 if (int_status & (DDR0_00_INT_STATUS_BIT0 | DDR0_00_INT_STATUS_BIT1)) { in get_ecc_status()
109 if (int_status & DDR0_00_INT_STATUS_BIT1) in get_ecc_status()
117 if (int_status & (DDR0_00_INT_STATUS_BIT2 | DDR0_00_INT_STATUS_BIT3)) { in get_ecc_status()
131 if (int_status & DDR0_00_INT_STATUS_BIT3) in get_ecc_status()
139 if (int_status & (DDR0_00_INT_STATUS_BIT4 | DDR0_00_INT_STATUS_BIT5)) { in get_ecc_status()
147 if (int_status & DDR0_00_INT_STATUS_BIT5) in get_ecc_status()
156 if (int_status & DDR0_00_INT_STATUS_BIT6) in get_ecc_status()
[all …]
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/post/cpu/ppc4xx/
H A Ddenali_ecc.c94 uint32_t int_status; in get_ecc_status() local
101 mfsdram(DDR0_00, int_status); in get_ecc_status()
102 int_status &= DDR0_00_INT_STATUS_MASK; in get_ecc_status()
105 if (int_status & (DDR0_00_INT_STATUS_BIT0 | DDR0_00_INT_STATUS_BIT1)) { in get_ecc_status()
109 if (int_status & DDR0_00_INT_STATUS_BIT1) in get_ecc_status()
117 if (int_status & (DDR0_00_INT_STATUS_BIT2 | DDR0_00_INT_STATUS_BIT3)) { in get_ecc_status()
131 if (int_status & DDR0_00_INT_STATUS_BIT3) in get_ecc_status()
139 if (int_status & (DDR0_00_INT_STATUS_BIT4 | DDR0_00_INT_STATUS_BIT5)) { in get_ecc_status()
147 if (int_status & DDR0_00_INT_STATUS_BIT5) in get_ecc_status()
156 if (int_status & DDR0_00_INT_STATUS_BIT6) in get_ecc_status()
[all …]
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/post/cpu/ppc4xx/
H A Ddenali_ecc.c94 uint32_t int_status; in get_ecc_status() local
101 mfsdram(DDR0_00, int_status); in get_ecc_status()
102 int_status &= DDR0_00_INT_STATUS_MASK; in get_ecc_status()
105 if (int_status & (DDR0_00_INT_STATUS_BIT0 | DDR0_00_INT_STATUS_BIT1)) { in get_ecc_status()
109 if (int_status & DDR0_00_INT_STATUS_BIT1) in get_ecc_status()
117 if (int_status & (DDR0_00_INT_STATUS_BIT2 | DDR0_00_INT_STATUS_BIT3)) { in get_ecc_status()
131 if (int_status & DDR0_00_INT_STATUS_BIT3) in get_ecc_status()
139 if (int_status & (DDR0_00_INT_STATUS_BIT4 | DDR0_00_INT_STATUS_BIT5)) { in get_ecc_status()
147 if (int_status & DDR0_00_INT_STATUS_BIT5) in get_ecc_status()
156 if (int_status & DDR0_00_INT_STATUS_BIT6) in get_ecc_status()
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/post/cpu/ppc4xx/
H A Ddenali_ecc.c94 uint32_t int_status; in get_ecc_status() local
101 mfsdram(DDR0_00, int_status); in get_ecc_status()
102 int_status &= DDR0_00_INT_STATUS_MASK; in get_ecc_status()
105 if (int_status & (DDR0_00_INT_STATUS_BIT0 | DDR0_00_INT_STATUS_BIT1)) { in get_ecc_status()
109 if (int_status & DDR0_00_INT_STATUS_BIT1) in get_ecc_status()
117 if (int_status & (DDR0_00_INT_STATUS_BIT2 | DDR0_00_INT_STATUS_BIT3)) { in get_ecc_status()
131 if (int_status & DDR0_00_INT_STATUS_BIT3) in get_ecc_status()
139 if (int_status & (DDR0_00_INT_STATUS_BIT4 | DDR0_00_INT_STATUS_BIT5)) { in get_ecc_status()
147 if (int_status & DDR0_00_INT_STATUS_BIT5) in get_ecc_status()
156 if (int_status & DDR0_00_INT_STATUS_BIT6) in get_ecc_status()
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