/dports/cad/digital/Digital-0.27/src/main/java/de/neemann/digital/core/element/ |
H A D | PinInfo.java | 52 private boolean isClock; // Is used only to draw the small triangle in front of the pins label. field in PinInfo 63 this.isClock=description.isClock(); in PinInfo() 163 public boolean isClock() { in isClock() method in PinInfo 164 return isClock; in isClock() 173 isClock = true; in setClock()
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H A D | PinDescription.java | 72 boolean isClock(); in isClock() method
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/dports/cad/openroad/OpenROAD-2.0/src/sta/search/ |
H A D | ClkNetwork.cc | 61 if (isClock(pin)) in deletePinBefore() 68 if (isClock(pin)) in disconnectPinBefore() 75 if (isClock(pin)) in connectPinAfter() 144 ClkNetwork::isClock(const Pin *pin) const in isClock() function in sta::ClkNetwork 150 ClkNetwork::isClock(const Net *net) const in isClock() function in sta::ClkNetwork 156 if (isClock(pin)) { in isClock()
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H A D | Tag.cc | 330 bool is_clk1 = tag1->isClock(); in tagCmp() 331 bool is_clk2 = tag2->isClock(); in tagCmp() 364 && tag1->isClock() == tag2->isClock() in tagEqual() 417 && tag1->isClock() == tag2->isClock() in tagMatch() 460 bool is_clk1 = tag1->isClock(); in tagMatchCmp() 461 bool is_clk2 = tag2->isClock(); in tagMatchCmp() 504 && tag1->isClock() == tag2->isClock() in tagMatchNoCrpr() 518 && tag1->isClock() == tag2->isClock() in tagMatchNoPathAp() 533 && tag1->isClock() == tag2->isClock() in tagMatchCrpr()
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H A D | GatedClk.cc | 80 && search_->isClock(gclk_vertex) in isGatedClkEnable() 81 && !search_->isClock(enable_vertex)) { in isGatedClkEnable() 93 && search_->isClock(graph_->pinLoadVertex(clk_pin))) { in isGatedClkEnable() 131 if (search_->isClock(gclk_vertex)) { in gatedClkEnables() 144 && !search_->isClock(graph_->pinLoadVertex(enable_pin))) { in gatedClkEnables()
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H A D | CheckTiming.cc | 101 if (!sdc_->isClock(pin)) { in checkNoInputDelay() 144 && search_->isClock(edge->from(graph_))) in hasClkedCheck() 290 && (!search_->isClock(edge->from(graph_)) in checkUnconstrainedSetups() 324 if (search_->isClock(vertex)) { in checkGeneratedClocks()
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H A D | Latches.cc | 242 if (path->isClock(this) in latchEnableOtherPath() 270 if (path->isClock(this) in latchEnablePath() 322 if (enable_path->isClock(this)) { in latchOutArrival() 439 && enable_path.isClock(this)) { in latchTimeGivenToStartpoint()
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H A D | CheckMaxSkews.cc | 206 if (clk_path->isClock(search)) { in visitMaxSkewChecks() 212 if (ref_path->isClock(search)) { in visitMaxSkewChecks()
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H A D | Path.cc | 82 Path::isClock(const StaState *sta) const in isClock() function in sta::Path 84 return tag(sta)->isClock(); in isClock()
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H A D | Tag.hh | 63 bool isClock() const { return is_clk_; } in isClock() function in sta::Tag
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H A D | VisitPathEnds.cc | 168 if (tgt_clk_path->isClock(this)) { in visitCheckEnd() 320 if (ref_path->isClock(this) in visitOutputDelayEnd() 413 if (clk_path->isClock(this) in visitGatedClkEnd()
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/dports/cad/digital/Digital-0.27/src/main/java/de/neemann/digital/hdl/model2/ |
H A D | HDLPort.java | 44 private boolean isClock; field in HDLPort 166 isClock = true; in setIsClock() 172 public boolean isClock() { in isClock() method in HDLPort 173 return isClock; in isClock()
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H A D | HDLNet.java | 205 public boolean isClock() { in isClock() method in HDLNet 208 return output.isClock(); in isClock()
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/dports/cad/digital/Digital-0.27/src/main/java/de/neemann/digital/hdl/model2/optimizations/ |
H A D | NodeSorterExpressionBased.java | 90 if (!net.isClock() && !nets.contains(net)) in visit() 112 if (!net.isClock() && nets.contains(net)) in visit() 124 if (!p.getNet().isClock() && !nets.contains(p.getNet())) in dependsOnlyOn() 131 if (!p.getNet().isClock() && nets.contains(p.getNet())) in dependsAtLeastAtOne()
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/dports/cad/openroad/OpenROAD-2.0/src/sta/include/sta/ |
H A D | ClkNetwork.hh | 41 bool isClock(const Pin *pin) const; 42 bool isClock(const Net *net) const;
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H A D | Path.hh | 53 virtual bool isClock(const StaState *sta) const;
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/dports/cad/librepcb/librepcb-0.1.6/libs/librepcb/library/cmp/ |
H A D | componentsignal.h | 69 bool isRequired, bool isNegated, bool isClock) noexcept; 80 bool isClock() const noexcept { return mIsClock; } in isClock() function
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H A D | componentsignal.cpp | 52 bool isNegated, bool isClock) noexcept in ComponentSignal() argument 60 mIsClock(isClock) { in ComponentSignal()
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/dports/astro/xtide/xtide-2.15.3/ |
H A D | xxClock.hh | 58 const bool isClock() const;
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H A D | xxPredictionWindow.hh | 73 virtual const bool isClock() const; // true if clock
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H A D | xxPredictionWindow.cc | 229 assert (!isClock()); in timestamp() 337 if (!isClock()) { in addNormalButtons() 441 const bool xxPredictionWindow::isClock() const { in isClock() function in xxPredictionWindow
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/dports/cad/librepcb/librepcb-0.1.6/libs/librepcb/library/cmp/cmd/ |
H A D | cmdcomponentsignaledit.cpp | 50 mOldIsClock(signal.isClock()), in CmdComponentSignalEdit()
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/dports/cad/openroad/OpenROAD-2.0/src/rsz/src/ |
H A D | Unused.cc | 123 && !isClock(net) in repairMaxFanout() 218 && !isClock(net) in repairMaxCap() 271 && !isClock(net) in repairMaxSlew() 527 && !search_->isClock(fanin_vertex)) { in repairTiming()
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/dports/biology/mrbayes/MrBayes-3.2.7/src/ |
H A D | sumpt.c | 2898 if (sumtParams.isClock == YES) in AddSumtPartition() 3079 if (sumtParams.isClock) in AllocPartCtr() 3227 t->isClock = sumtParams.isClock; in ConTree() 6335 if (sumtParams.tree->isClock) in DoSumtTree() 6516 sumtParams.isClock = t->isClock; in DoSumtTree() 6551 if (sumtParams.isClock != t->isClock) in DoSumtTree() 6593 if (t->isClock) in DoSumtTree() 7291 if (sumtParams.isClock == YES ) in PrintBrParamsToFile() 7512 if (sumtParams.isClock == YES) in PrintFigTreeNodeInfo() 7943 if (t->isClock == YES) in ShowConPhylogram() [all …]
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/dports/cad/digital/Digital-0.27/src/main/java/de/neemann/digital/hdl/vhdl2/ |
H A D | VHDLTestBenchCreator.java | 276 private void writeValues(Value[] values, boolean isClock, int clock) throws IOException { in writeValues() argument 285 if (isClock && dataOrder.get(i).getDirection() == HDLPort.Direction.IN) in writeValues()
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