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Searched refs:isClock (Results 1 – 25 of 70) sorted by relevance

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/dports/cad/digital/Digital-0.27/src/main/java/de/neemann/digital/core/element/
H A DPinInfo.java52 private boolean isClock; // Is used only to draw the small triangle in front of the pins label. field in PinInfo
63 this.isClock=description.isClock(); in PinInfo()
163 public boolean isClock() { in isClock() method in PinInfo
164 return isClock; in isClock()
173 isClock = true; in setClock()
H A DPinDescription.java72 boolean isClock(); in isClock() method
/dports/cad/openroad/OpenROAD-2.0/src/sta/search/
H A DClkNetwork.cc61 if (isClock(pin)) in deletePinBefore()
68 if (isClock(pin)) in disconnectPinBefore()
75 if (isClock(pin)) in connectPinAfter()
144 ClkNetwork::isClock(const Pin *pin) const in isClock() function in sta::ClkNetwork
150 ClkNetwork::isClock(const Net *net) const in isClock() function in sta::ClkNetwork
156 if (isClock(pin)) { in isClock()
H A DTag.cc330 bool is_clk1 = tag1->isClock(); in tagCmp()
331 bool is_clk2 = tag2->isClock(); in tagCmp()
364 && tag1->isClock() == tag2->isClock() in tagEqual()
417 && tag1->isClock() == tag2->isClock() in tagMatch()
460 bool is_clk1 = tag1->isClock(); in tagMatchCmp()
461 bool is_clk2 = tag2->isClock(); in tagMatchCmp()
504 && tag1->isClock() == tag2->isClock() in tagMatchNoCrpr()
518 && tag1->isClock() == tag2->isClock() in tagMatchNoPathAp()
533 && tag1->isClock() == tag2->isClock() in tagMatchCrpr()
H A DGatedClk.cc80 && search_->isClock(gclk_vertex) in isGatedClkEnable()
81 && !search_->isClock(enable_vertex)) { in isGatedClkEnable()
93 && search_->isClock(graph_->pinLoadVertex(clk_pin))) { in isGatedClkEnable()
131 if (search_->isClock(gclk_vertex)) { in gatedClkEnables()
144 && !search_->isClock(graph_->pinLoadVertex(enable_pin))) { in gatedClkEnables()
H A DCheckTiming.cc101 if (!sdc_->isClock(pin)) { in checkNoInputDelay()
144 && search_->isClock(edge->from(graph_))) in hasClkedCheck()
290 && (!search_->isClock(edge->from(graph_)) in checkUnconstrainedSetups()
324 if (search_->isClock(vertex)) { in checkGeneratedClocks()
H A DLatches.cc242 if (path->isClock(this) in latchEnableOtherPath()
270 if (path->isClock(this) in latchEnablePath()
322 if (enable_path->isClock(this)) { in latchOutArrival()
439 && enable_path.isClock(this)) { in latchTimeGivenToStartpoint()
H A DCheckMaxSkews.cc206 if (clk_path->isClock(search)) { in visitMaxSkewChecks()
212 if (ref_path->isClock(search)) { in visitMaxSkewChecks()
H A DPath.cc82 Path::isClock(const StaState *sta) const in isClock() function in sta::Path
84 return tag(sta)->isClock(); in isClock()
H A DTag.hh63 bool isClock() const { return is_clk_; } in isClock() function in sta::Tag
H A DVisitPathEnds.cc168 if (tgt_clk_path->isClock(this)) { in visitCheckEnd()
320 if (ref_path->isClock(this) in visitOutputDelayEnd()
413 if (clk_path->isClock(this) in visitGatedClkEnd()
/dports/cad/digital/Digital-0.27/src/main/java/de/neemann/digital/hdl/model2/
H A DHDLPort.java44 private boolean isClock; field in HDLPort
166 isClock = true; in setIsClock()
172 public boolean isClock() { in isClock() method in HDLPort
173 return isClock; in isClock()
H A DHDLNet.java205 public boolean isClock() { in isClock() method in HDLNet
208 return output.isClock(); in isClock()
/dports/cad/digital/Digital-0.27/src/main/java/de/neemann/digital/hdl/model2/optimizations/
H A DNodeSorterExpressionBased.java90 if (!net.isClock() && !nets.contains(net)) in visit()
112 if (!net.isClock() && nets.contains(net)) in visit()
124 if (!p.getNet().isClock() && !nets.contains(p.getNet())) in dependsOnlyOn()
131 if (!p.getNet().isClock() && nets.contains(p.getNet())) in dependsAtLeastAtOne()
/dports/cad/openroad/OpenROAD-2.0/src/sta/include/sta/
H A DClkNetwork.hh41 bool isClock(const Pin *pin) const;
42 bool isClock(const Net *net) const;
H A DPath.hh53 virtual bool isClock(const StaState *sta) const;
/dports/cad/librepcb/librepcb-0.1.6/libs/librepcb/library/cmp/
H A Dcomponentsignal.h69 bool isRequired, bool isNegated, bool isClock) noexcept;
80 bool isClock() const noexcept { return mIsClock; } in isClock() function
H A Dcomponentsignal.cpp52 bool isNegated, bool isClock) noexcept in ComponentSignal() argument
60 mIsClock(isClock) { in ComponentSignal()
/dports/astro/xtide/xtide-2.15.3/
H A DxxClock.hh58 const bool isClock() const;
H A DxxPredictionWindow.hh73 virtual const bool isClock() const; // true if clock
H A DxxPredictionWindow.cc229 assert (!isClock()); in timestamp()
337 if (!isClock()) { in addNormalButtons()
441 const bool xxPredictionWindow::isClock() const { in isClock() function in xxPredictionWindow
/dports/cad/librepcb/librepcb-0.1.6/libs/librepcb/library/cmp/cmd/
H A Dcmdcomponentsignaledit.cpp50 mOldIsClock(signal.isClock()), in CmdComponentSignalEdit()
/dports/cad/openroad/OpenROAD-2.0/src/rsz/src/
H A DUnused.cc123 && !isClock(net) in repairMaxFanout()
218 && !isClock(net) in repairMaxCap()
271 && !isClock(net) in repairMaxSlew()
527 && !search_->isClock(fanin_vertex)) { in repairTiming()
/dports/biology/mrbayes/MrBayes-3.2.7/src/
H A Dsumpt.c2898 if (sumtParams.isClock == YES) in AddSumtPartition()
3079 if (sumtParams.isClock) in AllocPartCtr()
3227 t->isClock = sumtParams.isClock; in ConTree()
6335 if (sumtParams.tree->isClock) in DoSumtTree()
6516 sumtParams.isClock = t->isClock; in DoSumtTree()
6551 if (sumtParams.isClock != t->isClock) in DoSumtTree()
6593 if (t->isClock) in DoSumtTree()
7291 if (sumtParams.isClock == YES ) in PrintBrParamsToFile()
7512 if (sumtParams.isClock == YES) in PrintFigTreeNodeInfo()
7943 if (t->isClock == YES) in ShowConPhylogram()
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/dports/cad/digital/Digital-0.27/src/main/java/de/neemann/digital/hdl/vhdl2/
H A DVHDLTestBenchCreator.java276 private void writeValues(Value[] values, boolean isClock, int clock) throws IOException { in writeValues() argument
285 if (isClock && dataOrder.get(i).getDirection() == HDLPort.Direction.IN) in writeValues()

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