/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AMDGPU/ |
H A D | AMDGPUCodeGenPrepare.cpp | 148 bool isI24(Value *V, unsigned ScalarSize) const; 427 bool AMDGPUCodeGenPrepare::isI24(Value *V, unsigned ScalarSize) const { in isI24() function in AMDGPUCodeGenPrepare 485 } else if (ST->hasMulI24() && isI24(LHS, Size) && isI24(RHS, Size)) { in replaceMulWithMul24()
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H A D | AMDGPUISelLowering.cpp | 2786 static bool isI24(SDValue Op, SelectionDAG &DAG) { in isI24() function 3340 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) { in performMulCombine() 3366 if (!isI24(N0, DAG) || !isI24(N1, DAG)) in performMulhsCombine()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUCodeGenPrepare.cpp | 148 bool isI24(Value *V, unsigned ScalarSize) const; 427 bool AMDGPUCodeGenPrepare::isI24(Value *V, unsigned ScalarSize) const { in isI24() function in AMDGPUCodeGenPrepare 485 } else if (ST->hasMulI24() && isI24(LHS, Size) && isI24(RHS, Size)) { in replaceMulWithMul24()
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H A D | AMDGPUISelLowering.cpp | 2786 static bool isI24(SDValue Op, SelectionDAG &DAG) { in isI24() function 3340 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) { in performMulCombine() 3366 if (!isI24(N0, DAG) || !isI24(N1, DAG)) in performMulhsCombine()
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUCodeGenPrepare.cpp | 148 bool isI24(Value *V, unsigned ScalarSize) const; 427 bool AMDGPUCodeGenPrepare::isI24(Value *V, unsigned ScalarSize) const { in isI24() function in AMDGPUCodeGenPrepare 485 } else if (ST->hasMulI24() && isI24(LHS, Size) && isI24(RHS, Size)) { in replaceMulWithMul24()
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H A D | AMDGPUISelLowering.cpp | 2786 static bool isI24(SDValue Op, SelectionDAG &DAG) { in isI24() function 3340 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) { in performMulCombine() 3366 if (!isI24(N0, DAG) || !isI24(N1, DAG)) in performMulhsCombine()
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/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AMDGPU/ |
H A D | AMDGPUCodeGenPrepare.cpp | 140 bool isI24(Value *V, unsigned ScalarSize) const; 419 bool AMDGPUCodeGenPrepare::isI24(Value *V, unsigned ScalarSize) const { in isI24() function in AMDGPUCodeGenPrepare 477 } else if (ST->hasMulI24() && isI24(LHS, Size) && isI24(RHS, Size)) { in replaceMulWithMul24()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUCodeGenPrepare.cpp | 175 bool isI24(Value *V, unsigned ScalarSize) const; 477 bool AMDGPUCodeGenPrepare::isI24(Value *V, unsigned ScalarSize) const { in isI24() function in AMDGPUCodeGenPrepare 535 } else if (ST->hasMulI24() && isI24(LHS, Size) && isI24(RHS, Size)) { in replaceMulWithMul24()
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H A D | AMDGPUISelLowering.cpp | 2780 static bool isI24(SDValue Op, SelectionDAG &DAG) { in isI24() function 3342 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) { in performMulCombine() 3368 if (!isI24(N0, DAG) || !isI24(N1, DAG)) in performMulhsCombine()
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUCodeGenPrepare.cpp | 168 bool isI24(Value *V, unsigned ScalarSize) const; 467 bool AMDGPUCodeGenPrepare::isI24(Value *V, unsigned ScalarSize) const { in isI24() function in AMDGPUCodeGenPrepare 525 } else if (ST->hasMulI24() && isI24(LHS, Size) && isI24(RHS, Size)) { in replaceMulWithMul24()
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H A D | AMDGPUISelLowering.cpp | 2771 static bool isI24(SDValue Op, SelectionDAG &DAG) { in isI24() function 3337 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) { in performMulCombine() 3363 if (!isI24(N0, DAG) || !isI24(N1, DAG)) in performMulhsCombine()
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUCodeGenPrepare.cpp | 154 bool isI24(Value *V, unsigned ScalarSize) const; 457 bool AMDGPUCodeGenPrepare::isI24(Value *V, unsigned ScalarSize) const { in isI24() function in AMDGPUCodeGenPrepare 515 } else if (ST->hasMulI24() && isI24(LHS, Size) && isI24(RHS, Size)) { in replaceMulWithMul24()
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H A D | AMDGPUISelLowering.cpp | 2877 static bool isI24(SDValue Op, SelectionDAG &DAG) { in isI24() function 3444 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) { in performMulCombine() 3479 if (!isI24(N0, DAG) || !isI24(N1, DAG)) in performMulhsCombine()
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AMDGPU/ |
H A D | AMDGPUCodeGenPrepare.cpp | 154 bool isI24(Value *V, unsigned ScalarSize) const; 457 bool AMDGPUCodeGenPrepare::isI24(Value *V, unsigned ScalarSize) const { in isI24() function in AMDGPUCodeGenPrepare 515 } else if (ST->hasMulI24() && isI24(LHS, Size) && isI24(RHS, Size)) { in replaceMulWithMul24()
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H A D | AMDGPUISelLowering.cpp | 2877 static bool isI24(SDValue Op, SelectionDAG &DAG) { in isI24() function 3444 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) { in performMulCombine() 3479 if (!isI24(N0, DAG) || !isI24(N1, DAG)) in performMulhsCombine()
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUCodeGenPrepare.cpp | 153 bool isI24(Value *V, unsigned ScalarSize) const; 455 bool AMDGPUCodeGenPrepare::isI24(Value *V, unsigned ScalarSize) const { in isI24() function in AMDGPUCodeGenPrepare 513 } else if (ST->hasMulI24() && isI24(LHS, Size) && isI24(RHS, Size)) { in replaceMulWithMul24()
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H A D | AMDGPUISelLowering.cpp | 2783 static bool isI24(SDValue Op, SelectionDAG &DAG) { in isI24() function 3345 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) { in performMulCombine() 3371 if (!isI24(N0, DAG) || !isI24(N1, DAG)) in performMulhsCombine()
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/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AMDGPU/ |
H A D | AMDGPUCodeGenPrepare.cpp | 168 bool isI24(Value *V, unsigned ScalarSize) const; 467 bool AMDGPUCodeGenPrepare::isI24(Value *V, unsigned ScalarSize) const { in isI24() function in AMDGPUCodeGenPrepare 525 } else if (ST->hasMulI24() && isI24(LHS, Size) && isI24(RHS, Size)) { in replaceMulWithMul24()
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUCodeGenPrepare.cpp | 154 bool isI24(Value *V, unsigned ScalarSize) const; 457 bool AMDGPUCodeGenPrepare::isI24(Value *V, unsigned ScalarSize) const { in isI24() function in AMDGPUCodeGenPrepare 515 } else if (ST->hasMulI24() && isI24(LHS, Size) && isI24(RHS, Size)) { in replaceMulWithMul24()
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUCodeGenPrepare.cpp | 154 bool isI24(Value *V, unsigned ScalarSize) const; 457 bool AMDGPUCodeGenPrepare::isI24(Value *V, unsigned ScalarSize) const { in isI24() function in AMDGPUCodeGenPrepare 515 } else if (ST->hasMulI24() && isI24(LHS, Size) && isI24(RHS, Size)) { in replaceMulWithMul24()
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUCodeGenPrepare.cpp | 154 bool isI24(Value *V, unsigned ScalarSize) const; 457 bool AMDGPUCodeGenPrepare::isI24(Value *V, unsigned ScalarSize) const { in isI24() function in AMDGPUCodeGenPrepare 515 } else if (ST->hasMulI24() && isI24(LHS, Size) && isI24(RHS, Size)) { in replaceMulWithMul24()
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUCodeGenPrepare.cpp | 153 bool isI24(Value *V, unsigned ScalarSize) const; 455 bool AMDGPUCodeGenPrepare::isI24(Value *V, unsigned ScalarSize) const { in isI24() function in AMDGPUCodeGenPrepare 513 } else if (ST->hasMulI24() && isI24(LHS, Size) && isI24(RHS, Size)) { in replaceMulWithMul24()
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUCodeGenPrepare.cpp | 154 bool isI24(Value *V, unsigned ScalarSize) const; 457 bool AMDGPUCodeGenPrepare::isI24(Value *V, unsigned ScalarSize) const { in isI24() function in AMDGPUCodeGenPrepare 515 } else if (ST->hasMulI24() && isI24(LHS, Size) && isI24(RHS, Size)) { in replaceMulWithMul24()
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/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 2665 static bool isI24(SDValue Op, SelectionDAG &DAG) { in isI24() function 3170 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) { in performMulCombine() 3196 if (!isI24(N0, DAG) || !isI24(N1, DAG)) in performMulhsCombine()
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/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 2713 static bool isI24(SDValue Op, SelectionDAG &DAG) { in isI24() function 3228 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) { in performMulCombine() 3254 if (!isI24(N0, DAG) || !isI24(N1, DAG)) in performMulhsCombine()
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