Home
last modified time | relevance | path

Searched refs:isNullReg (Results 1 – 25 of 30) sorted by relevance

12

/dports/devel/intel-graphics-compiler/intel-graphics-compiler-igc-1.0.9636/visa/VisaToG4/
H A DTranslateMisc.cpp158 if (!source->isNullReg()) { in Copy_Source_To_Payload()
187 if (srcReg->isNullReg()) { in preparePayload()
328 allNull &= src->isNullReg(); in coalescePayload()
329 onlySrc0NonNull &= ix++ == 0 || src->isNullReg(); in coalescePayload()
353 if (src && !src->isNullReg()) in coalescePayload()
366 if (src && !src->isNullReg()) { in coalescePayload()
H A DTranslateSend3D.cpp327 if (channelMask->isNullReg()) in translateVISAURBWrite3DInst()
857 if (R->isNullReg() || in translateVISARTWrite3DInst()
858 G->isNullReg() || in translateVISARTWrite3DInst()
859 B->isNullReg() || in translateVISARTWrite3DInst()
860 A->isNullReg()) in translateVISARTWrite3DInst()
958 if (!R->isNullReg()) in translateVISARTWrite3DInst()
963 if (!G->isNullReg()) in translateVISARTWrite3DInst()
968 if (!B->isNullReg()) in translateVISARTWrite3DInst()
973 if (!A->isNullReg()) in translateVISARTWrite3DInst()
1386 if (!dst->isNullReg()) in splitSampleInst()
[all …]
H A DTranslateSendLdStLsc.cpp48 MUST_BE_TRUE(surface->isNullReg() || in lscTryPromoteSurfaceImmToExDesc()
62 return opnd == nullptr || opnd->isNullReg(); in isNullOperand()
334 if (dstRead->isNullReg()) { in translateLscUntypedInst()
646 if (srcAddr == nullptr || srcAddr->isNullReg()) { in translateLscTypedInst()
703 if (data == nullptr || data->isNullReg()) { in translateLscTypedInst()
716 if (!srcData->isNullReg()) { in translateLscTypedInst()
723 opInfo.isLoad() || (opInfo.isAtomic() && !dstData->isNullReg()) ? in translateLscTypedInst()
738 if (opInfo.isLoad() || (opInfo.isAtomic() && !dstData->isNullReg())) { in translateLscTypedInst()
H A DTranslateSendLdStLegacy.cpp1467 bool hasRet = !dst->isNullReg(); in translateVISADwordAtomicInst()
1496 if (src0 && !src0->isNullReg()) { in translateVISADwordAtomicInst()
1503 if (src1 && !src1->isNullReg()) { in translateVISADwordAtomicInst()
1592 if (!vOffsetOpnd->isNullReg()) { in buildTypedSurfaceAddressPayload()
1598 else if (!lodOpnd->isNullReg()) { in buildTypedSurfaceAddressPayload()
1607 if (!rOffsetOpnd->isNullReg()) { in buildTypedSurfaceAddressPayload()
1608 ASSERT_USER(!vOffsetOpnd->isNullReg(), in buildTypedSurfaceAddressPayload()
1615 else if (!lodOpnd->isNullReg()) { in buildTypedSurfaceAddressPayload()
1624 if (!lodOpnd->isNullReg()) { in buildTypedSurfaceAddressPayload()
2981 if (src0 != NULL && !src0->isNullReg()) in translateVISASVMAtomicInst()
[all …]
H A DTranslateSendRaw.cpp143 if (!dstOpnd->isNullReg()) { in translateVISARawSendsInst()
H A DTranslateALU.cpp195 if (src0Opnd->isNullReg()) in translateVISADpasInst()
/dports/devel/intel-graphics-compiler/intel-graphics-compiler-igc-1.0.9636/visa/
H A DG4_Verifier.cpp285 if (src != NULL && !src->isNullReg() && src->getTopDcl() && in verifyDstSrcOverlap()
315 if (src->isNullReg()) in verifySend()
348 if (!dst->isNullReg()) in verifySend()
356 if (src1 && !src1->isNullReg()) in verifySend()
399 opnd->isNullReg() == false && in verifyOpnd()
434 if (opnd->isRightBoundSet() && !opnd->isNullReg()) in verifyOpnd()
1124 (!src0->isNullReg() && !isSrcRegion110(src0->getRegion())) || in verifyDpas()
1275 if (dst && !dst->isNullReg() && !I->isCompare()) in verifyBFMixedMode()
1283 if (src && !src->isNullReg()) in verifyBFMixedMode()
1374 if (dreg && !dreg->isNullReg() && !inst->isCompare()) in verifyBFMixedMode()
[all …]
H A DG4_IR.hpp2289 bool isNullReg() const;
2422 if (isRightBoundSet() == false && !isNullReg()) in getLeftBound()
2566 bool isNullReg() const;
2902 bool isNullReg() const { return (reg.phyReg != NULL) && (reg.phyReg->isNullReg()); } in isNullReg() function in vISA::G4_RegVar
3137 bool isNullReg() const { return base->isNullReg(); } in isNullReg() function in vISA::G4_SrcRegRegion
3294 if (isNullReg()) in isCrossGRFDst()
3320 bool isNullReg() const { return base->isNullReg(); } in isNullReg() function in vISA::G4_DstRegRegion
3674 inline bool G4_Operand::isNullReg() const in isNullReg() function in vISA::G4_Operand
3750 inline bool G4_VarBase::isNullReg() const in isNullReg() function in vISA::G4_VarBase
3753 return asRegVar()->isNullReg(); in isNullReg()
[all …]
H A DInstSplit.cpp102 if (dst->isNullReg()) in splitInstruction()
182 if (needSplitByExecSize(execSize) && inst->getDst()->isNullReg() && in splitInstruction()
273 (inst->opcode() == G4_math && j == 1 && src->isNullReg())) in splitInstruction()
H A DRematerialization.cpp27 if (dst && !dst->isNullReg()) in populateRefs()
395 if (currDst && !currDst->isNullReg()) in checkLocalWAR()
405 !(srcOpnd->isNullReg()) && in checkLocalWAR()
680 if (!srcOpnd || srcOpnd->isImm() || srcOpnd->isNullReg()) in canRematerialize()
H A DHWConformity.cpp665 bool nullSrc1 = src1 && src1->isNullReg(); in fixMathInst()
758 if (dst->isNullReg()) in hasSameSubregOffset()
1398 if (dst && dst->isNullReg()) in fixCompareInst()
1810 !inst->getDst()->isNullReg() && in fixPredicateIndirectInst()
3559 if (dst != NULL && !dst->isNullReg()) in fix64bInst()
5129 if (!dst->isNullReg()) in fixSendInst()
5214 !src1->isNullReg() && !src2->isNullReg() && in fixsrc1src2Overlap()
5349 dst->isNullReg() || in avoidInstDstSrcOverlap()
6027 if (src && !src->isNullReg()) in fixBFMixedMode()
8333 if (inst->getDst()->isNullReg()) in fixUnalignedRegions()
[all …]
H A DLocalDataflow.cpp440 if (opnd == nullptr || opnd->isImm() || opnd->isNullReg() || opnd->isLabel()) in processReadOpnds()
470 if (opnd == nullptr || opnd->isNullReg()) in processWriteOpnds()
H A DReduceExecSize.cpp554 !(inst->opcode() == G4_math && i == 1 && srcs[i]->isNullReg())) in reduceExecSize()
941 (inst->opcode() == G4_math && j == 1 && srcs[j]->isNullReg())) in splitSIMD32Inst()
1056 srcs[j]->isNullReg() || (j == 0 && op == G4_line)) in splitInstruction()
1164 (inst->opcode() == G4_math && j == 1 && srcs[j]->isNullReg())) in splitInstruction()
1383 if (srcs[j]->isImm() || srcs[j]->isNullReg()) in evenlySplitInst()
H A DG4_IR.cpp2988 if (dst && dst->isNullReg()) in hasNULLDst()
3133 bool NULLSrc1 = (opcode() == G4_math && src1_1->isNullReg()); in isRAWdep()
4498 if (!baseVar->isNullReg()) in printRegVarOff()
4539 …if (!base->isNullReg() && !base->isIpReg() && !base->isNReg() && subRegOff != (short) UNDEFINED_SH… in printRegVarOff()
4625 …if (desc && !base->isNullReg() && !base->isNReg() && !isAccRegValid())// rgn == NULL, the default … in emit()
5512 else if (base->isNullReg()) in emit()
7023 opnd->isNullReg() == false) in computeRightBound()
7111 if (opnd && !opnd->isImm() && !opnd->isNullReg()) in computeRightBound()
8708 if (opnd && !opnd->isImm() && !opnd->isNullReg()) in computeRightBound()
8721 if (opnd == dst || (opnd == srcs[0] && !opnd->isNullReg())) in computeRightBound()
H A DOptimizer.cpp868 !inst->getDst()->isNullReg()) in insertDummyMovForHWRSWADPAS()
917 !inst->getDst()->isNullReg()) in insertDummyMovForHWRSWA()
1388 if (dst && !dst->isNullReg()) in replaceAllSpilledRegions()
2496 !defInst->getDst()->isNullReg()) in checkLifetime()
7384 if (src[i] && !src[i]->isNullReg()) in evenlySplitDPASInst()
7411 else if (src[i]->isNullReg()) in evenlySplitDPASInst()
11810 if (Opnd == nullptr || Opnd->isNullReg()) in isDeadInst()
11900 if (A == nullptr || A->isNullReg() || !A->isGreg()) in retires()
11957 if (!Dst->isNullReg() && !Dst->isIndirect() && Dst->isGreg()) in retireSends()
11962 if (Opnd == nullptr || !Opnd->isSrcRegRegion() || Opnd->isNullReg()) in retireSends()
[all …]
H A DBinaryEncodingCNL.cpp855 if (inst->isMath() && src1->isNullReg() && !src0->isImm()) in EncodeTwoSrcInst()
867 else if (!(inst->isMath() && src1->isNullReg() && src0->isImm())) in EncodeTwoSrcInst()
885 MUST_BE_TRUE(src1->isNullReg(), "src1 must be null ARF if src0 is immediate"); in EncodeTwoSrcInst()
H A DSpillCleanup.cpp1166 if (!inst->getDst()->isNullReg()) in populateSendDstDcl()
1468 !inst->getDst()->isNullReg() && in removeRedundantSplitMovs()
H A DLinearScanRA.cpp556 if (curInst->isSplitSend() && !curInst->getSrc(1)->isNullReg()) in linearScanMarkReferences()
1499 if (src == nullptr || src->isNullReg()) in calculateInputIntervalsGlobal()
1713 if (src == nullptr || src->isNullReg()) in calculateCurrentBBLiveIntervals()
H A DBinaryEncodingIGA.cpp274 if (src0->isNullReg()) { in getIGADpasType()
1329 srcRegion->isNullReg() ? NOACC : srcRegion->getAccRegSel(); in translateInstructionSrcs()
H A DLoopAnalysis.cpp1327 if (dst && !dst->isNullReg()) in run()
H A DGraphColor.cpp2459 if ((inst->isSend() || inst->isFillIntrinsic()) && !dst->isNullReg() && in buildInterferenceWithinBB()
2464 else if (kernel.fg.builder->avoidDstSrcOverlap() && dst && !dst->isNullReg()) in buildInterferenceWithinBB()
2469 if ((inst->isSend() || inst->isFillIntrinsic()) && !dst->isNullReg()) in buildInterferenceWithinBB()
2483 if (inst->isSplitSend() && !inst->getSrc(1)->isNullReg()) in buildInterferenceWithinBB()
2503 if (inst->isDpas() && !inst->getSrc(1)->isNullReg()) in buildInterferenceWithinBB()
5597 …_i->isGreg() || gra.isUndefinedDcl(lrs[i]->getDcl()) || lrs[i]->getDcl()->getRegVar()->isNullReg()) in linearScanVerify()
5610 …) || builder.kernel.fg.isPseudoDcl(lrs[j]->getDcl()) || lrs[j]->getDcl()->getRegVar()->isNullReg()) in linearScanVerify()
10749 if (inst->isSend() && !inst->getDst()->isNullReg()) in replaceWithPreDcl()
11918 (inst->opcode() == G4_math && j == 1 && curr_src->isNullReg()) || in computePhyReg()
H A DG4_BB.cpp1375 if (!inst->getDst() || inst->getDst()->isNullReg() || in countReadModifyWrite()
H A DRegAlloc.cpp126 …if (dst && !dst->isNullReg() && dst->getBase()->asRegVar()->getDeclare()->getRegFile() == G4_SCALA… in doPointsToAnalysis()
165 if (!src || src->isNullReg()) in doPointsToAnalysis()
/dports/devel/intel-graphics-compiler/intel-graphics-compiler-igc-1.0.9636/visa/LocalScheduler/
H A DG4_Sched.cpp2036 if (opnd == nullptr || opnd->getBase() == nullptr || opnd->isNullReg()) in processBarrier()
2129 if (opnd == nullptr || opnd->getBase() == nullptr || opnd->isNullReg()) in processReadWrite()
2172 if (opnd == nullptr || opnd->getBase() == nullptr || opnd->isNullReg()) in processReadWrite()
H A DSWSB_G4IR.cpp125 if (msgDesc->isRead() && (inst->getDst() == nullptr || inst->getDst()->isNullReg())) in isPrefetch()
1326 inst->getDst()->isNullReg()) in calcDepDelayForNode()
4732 … isSLMMsg(liveInst) && liveInst->getDst() != nullptr && !liveInst->getDst()->isNullReg()) in setSendOpndMayKilled()
5122 … isSLMMsg(liveInst) && liveInst->getDst() != nullptr && !liveInst->getDst()->isNullReg()) in clearSLMWARWAissue()
5534 if (!inst->getDst() || inst->getDst()->isNullReg()) in is2xDPBlockCandidate()
7113 !node->GetInstruction()->getDst()->isNullReg()) in addGlobalDependenceWithReachingDef()
7577 if (!opnd || !opnd->getBase() || opnd->isNullReg()) in setForceDebugSWSB()
7681 if (!opnd || !opnd->getBase() || opnd->isNullReg()) in setInstructionStallSWSB()

12