/dports/devel/py-keystone-engine/keystone-engine-0.9.1-3/src/llvm/include/llvm/MC/ |
H A D | MCInstrDesc.h | 219 bool isPredicable() const { return Flags & (1 << MCID::Predicable); } in isPredicable() function 311 if (isPredicable()) { in findFirstPredOperandIdx()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/Hexagon/ |
H A D | HexagonPseudo.td | 161 let isCall = 1, hasSideEffects = 1, isPredicable = 0, 178 isPredicable = 0 in 207 let isPredicable = 0; // !if(isPred, 0, 1); 220 isPredicable = 1, hasSideEffects = 0, InputType = "reg", 234 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in 238 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 244 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 337 isPredicable = 1, 353 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonPseudo.td | 161 let isCall = 1, hasSideEffects = 1, isPredicable = 0, 178 isPredicable = 0 in 207 let isPredicable = 0; // !if(isPred, 0, 1); 220 isPredicable = 1, hasSideEffects = 0, InputType = "reg", 234 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in 238 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 244 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 337 isPredicable = 1, 353 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/Hexagon/ |
H A D | HexagonPseudo.td | 161 let isCall = 1, hasSideEffects = 1, isPredicable = 0, 178 isPredicable = 0 in 207 let isPredicable = 0; // !if(isPred, 0, 1); 220 isPredicable = 1, hasSideEffects = 0, InputType = "reg", 234 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in 238 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 244 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 337 isPredicable = 1, 353 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
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/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/Hexagon/ |
H A D | HexagonPseudo.td | 161 let isCall = 1, hasSideEffects = 1, isPredicable = 0, 178 isPredicable = 0 in 207 let isPredicable = 0; // !if(isPred, 0, 1); 220 isPredicable = 1, hasSideEffects = 0, InputType = "reg", 234 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in 238 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 244 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 337 isPredicable = 1, 353 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/ |
H A D | HexagonPseudo.td | 161 let isCall = 1, hasSideEffects = 1, isPredicable = 0, 178 isPredicable = 0 in 207 let isPredicable = 0; // !if(isPred, 0, 1); 220 isPredicable = 1, hasSideEffects = 0, InputType = "reg", 234 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in 238 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 244 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 337 isPredicable = 1, 353 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/Hexagon/ |
H A D | HexagonPseudo.td | 161 let isCall = 1, hasSideEffects = 1, isPredicable = 0, 178 isPredicable = 0 in 207 let isPredicable = 0; // !if(isPred, 0, 1); 220 isPredicable = 1, hasSideEffects = 0, InputType = "reg", 234 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in 238 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 244 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 337 isPredicable = 1, 353 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/Hexagon/ |
H A D | HexagonPseudo.td | 161 let isCall = 1, hasSideEffects = 1, isPredicable = 0, 178 isPredicable = 0 in 207 let isPredicable = 0; // !if(isPred, 0, 1); 220 isPredicable = 1, hasSideEffects = 0, InputType = "reg", 234 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in 238 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 244 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 337 isPredicable = 1, 353 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
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/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/Hexagon/ |
H A D | HexagonPseudo.td | 161 let isCall = 1, hasSideEffects = 1, isPredicable = 0, 178 isPredicable = 0 in 207 let isPredicable = 0; // !if(isPred, 0, 1); 220 isPredicable = 1, hasSideEffects = 0, InputType = "reg", 234 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in 238 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 244 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 337 isPredicable = 1, 353 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
H A D | HexagonPseudo.td | 161 let isCall = 1, hasSideEffects = 1, isPredicable = 0, 178 isPredicable = 0 in 207 let isPredicable = 0; // !if(isPred, 0, 1); 220 isPredicable = 1, hasSideEffects = 0, InputType = "reg", 234 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in 238 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 244 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 337 isPredicable = 1, 353 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonPseudo.td | 161 let isCall = 1, hasSideEffects = 1, isPredicable = 0, 178 isPredicable = 0 in 207 let isPredicable = 0; // !if(isPred, 0, 1); 220 isPredicable = 1, hasSideEffects = 0, InputType = "reg", 234 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in 238 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 244 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 337 isPredicable = 1, 353 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/Hexagon/ |
H A D | HexagonPseudo.td | 161 let isCall = 1, hasSideEffects = 1, isPredicable = 0, 178 isPredicable = 0 in 207 let isPredicable = 0; // !if(isPred, 0, 1); 220 isPredicable = 1, hasSideEffects = 0, InputType = "reg", 234 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in 238 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 244 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 337 isPredicable = 1, 353 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/ |
H A D | HexagonPseudo.td | 161 let isCall = 1, hasSideEffects = 1, isPredicable = 0, 178 isPredicable = 0 in 207 let isPredicable = 0; // !if(isPred, 0, 1); 220 isPredicable = 1, hasSideEffects = 0, InputType = "reg", 234 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in 238 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 244 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 337 isPredicable = 1, 353 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/Hexagon/ |
H A D | HexagonPseudo.td | 161 let isCall = 1, hasSideEffects = 1, isPredicable = 0, 178 isPredicable = 0 in 207 let isPredicable = 0; // !if(isPred, 0, 1); 220 isPredicable = 1, hasSideEffects = 0, InputType = "reg", 234 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in 238 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 244 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 337 isPredicable = 1, 353 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/ |
H A D | HexagonPseudo.td | 161 let isCall = 1, hasSideEffects = 1, isPredicable = 0, 178 isPredicable = 0 in 207 let isPredicable = 0; // !if(isPred, 0, 1); 220 isPredicable = 1, hasSideEffects = 0, InputType = "reg", 234 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in 238 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 244 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 337 isPredicable = 1, 353 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
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/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/Hexagon/ |
H A D | HexagonPseudo.td | 161 let isCall = 1, hasSideEffects = 1, isPredicable = 0, 178 isPredicable = 0 in 207 let isPredicable = 0; // !if(isPred, 0, 1); 220 isPredicable = 1, hasSideEffects = 0, InputType = "reg", 234 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in 238 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 244 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 337 isPredicable = 1, 353 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
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/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/Hexagon/ |
H A D | HexagonPseudo.td | 162 let isCall = 1, hasSideEffects = 1, isPredicable = 0, 179 isPredicable = 0 in 208 let isPredicable = 0; // !if(isPred, 0, 1); 221 isPredicable = 1, hasSideEffects = 0, InputType = "reg", 235 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in 239 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 245 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 338 isPredicable = 1, 354 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
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/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/Hexagon/ |
H A D | HexagonPseudo.td | 162 let isCall = 1, hasSideEffects = 1, isPredicable = 0, 179 isPredicable = 0 in 208 let isPredicable = 0; // !if(isPred, 0, 1); 220 isPredicable = 1, hasSideEffects = 0, InputType = "reg", 234 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in 238 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 244 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 337 isPredicable = 1, 353 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
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/dports/devel/llvm90/llvm-9.0.1.src/include/llvm/MC/ |
H A D | MCInstrDesc.h | 308 bool isPredicable() const { return Flags & (1ULL << MCID::Predicable); } in isPredicable() function 592 if (isPredicable()) { in findFirstPredOperandIdx()
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/dports/devel/llvm80/llvm-8.0.1.src/include/llvm/MC/ |
H A D | MCInstrDesc.h | 308 bool isPredicable() const { return Flags & (1ULL << MCID::Predicable); } in isPredicable() function 587 if (isPredicable()) { in findFirstPredOperandIdx()
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/dports/devel/llvm70/llvm-7.0.1.src/include/llvm/MC/ |
H A D | MCInstrDesc.h | 306 bool isPredicable() const { return Flags & (1ULL << MCID::Predicable); } in isPredicable() function 580 if (isPredicable()) { in findFirstPredOperandIdx()
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/dports/security/clamav-lts/clamav-0.103.5/libclamav/c++/llvm/lib/Target/ |
H A D | TargetInstrInfo.cpp | 65 if (!TID.isPredicable()) in isUnpredicatedTerminator()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/include/llvm/MC/ |
H A D | MCInstrDesc.h | 321 bool isPredicable() const { return Flags & (1ULL << MCID::Predicable); } in isPredicable() function 614 if (isPredicable()) { in findFirstPredOperandIdx()
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/include/llvm/MC/ |
H A D | MCInstrDesc.h | 329 bool isPredicable() const { return Flags & (1ULL << MCID::Predicable); } in isPredicable() function 622 if (isPredicable()) { in findFirstPredOperandIdx()
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/include/llvm/MC/ |
H A D | MCInstrDesc.h | 330 bool isPredicable() const { return Flags & (1ULL << MCID::Predicable); } in isPredicable() function 623 if (isPredicable()) { in findFirstPredOperandIdx()
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