| /dports/devel/llvm80/llvm-8.0.1.src/lib/Target/AMDGPU/ |
| H A D | GCNHazardRecognizer.cpp | 434 if (!Use.isReg() || TRI.isVGPR(MF.getRegInfo(), Use.getReg())) in checkVMEMHazards()
455 if (!Use.isReg() || !TRI->isVGPR(MF.getRegInfo(), Use.getReg())) in checkDPPHazards()
565 if (!TRI->isVGPR(MRI, Def.getReg())) in checkVALUHazardsHelper()
672 if (!Use.isReg() || TRI->isVGPR(MF.getRegInfo(), Use.getReg())) in checkAnyInstHazards()
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| H A D | SIInsertWaitcnts.cpp | 468 if (TRI->isVGPR(MRIA, Op.getReg())) { in getRegInterval()
499 assert(TRI->isVGPR(*MRI, Opnd.getReg())); in setExpScore()
564 if (Op.isReg() && !Op.isDef() && TRI->isVGPR(MRIA, Op.getReg())) { in updateByEvent()
612 TRI->isVGPR(MRIA, DefMO.getReg())) { in updateByEvent()
620 if (MO.isReg() && !MO.isDef() && TRI->isVGPR(MRIA, MO.getReg())) { in updateByEvent()
948 if (TRI->isVGPR(MRIA, Op.getReg())) { in generateWaitcntInstBefore()
984 if (TRI->isVGPR(MRIA, Def.getReg())) { in generateWaitcntInstBefore()
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/Target/AMDGPU/ |
| H A D | GCNHazardRecognizer.cpp | 413 if (!Use.isReg() || TRI.isVGPR(MF.getRegInfo(), Use.getReg())) in checkVMEMHazards()
434 if (!Use.isReg() || !TRI->isVGPR(MF.getRegInfo(), Use.getReg())) in checkDPPHazards()
544 if (!TRI->isVGPR(MRI, Def.getReg())) in checkVALUHazardsHelper()
651 if (!Use.isReg() || TRI->isVGPR(MF.getRegInfo(), Use.getReg())) in checkAnyInstHazards()
|
| H A D | SIShrinkInstructions.cpp | 87 if (!Src1->isReg() || !TRI.isVGPR(MRI, Src1->getReg()))
95 if (!Src2->isReg() || !TRI.isVGPR(MRI, Src2->getReg()) ||
106 if (Src1 && (!Src1->isReg() || !TRI.isVGPR(MRI, Src1->getReg()) ||
|
| /dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 209 bool isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const;
212 return isVGPR(MRI, Reg) || isAGPR(MRI, Reg); in isVectorRegister()
|
| H A D | GCNHazardRecognizer.cpp | 592 if (!Use.isReg() || TRI.isVGPR(MF.getRegInfo(), Use.getReg())) in checkVMEMHazards()
614 if (!Use.isReg() || !TRI->isVGPR(MF.getRegInfo(), Use.getReg())) in checkDPPHazards()
727 if (!TRI->isVGPR(MRI, Def.getReg())) in checkVALUHazardsHelper()
835 if (!Use.isReg() || TRI->isVGPR(MF.getRegInfo(), Use.getReg())) in checkAnyInstHazards()
1220 if (!Use.isReg() || !TRI.isVGPR(MF.getRegInfo(), Use.getReg())) in checkMAIHazards()
1377 if (!Op.isReg() || !TRI.isVGPR(MF.getRegInfo(), Op.getReg())) in checkMAILdStHazards()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 209 bool isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const;
212 return isVGPR(MRI, Reg) || isAGPR(MRI, Reg); in isVectorRegister()
|
| H A D | GCNHazardRecognizer.cpp | 592 if (!Use.isReg() || TRI.isVGPR(MF.getRegInfo(), Use.getReg())) in checkVMEMHazards()
614 if (!Use.isReg() || !TRI->isVGPR(MF.getRegInfo(), Use.getReg())) in checkDPPHazards()
727 if (!TRI->isVGPR(MRI, Def.getReg())) in checkVALUHazardsHelper()
835 if (!Use.isReg() || TRI->isVGPR(MF.getRegInfo(), Use.getReg())) in checkAnyInstHazards()
1220 if (!Use.isReg() || !TRI.isVGPR(MF.getRegInfo(), Use.getReg())) in checkMAIHazards()
1377 if (!Op.isReg() || !TRI.isVGPR(MF.getRegInfo(), Op.getReg())) in checkMAILdStHazards()
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 209 bool isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const;
212 return isVGPR(MRI, Reg) || isAGPR(MRI, Reg); in isVectorRegister()
|
| H A D | GCNHazardRecognizer.cpp | 592 if (!Use.isReg() || TRI.isVGPR(MF.getRegInfo(), Use.getReg())) in checkVMEMHazards()
614 if (!Use.isReg() || !TRI->isVGPR(MF.getRegInfo(), Use.getReg())) in checkDPPHazards()
727 if (!TRI->isVGPR(MRI, Def.getReg())) in checkVALUHazardsHelper()
835 if (!Use.isReg() || TRI->isVGPR(MF.getRegInfo(), Use.getReg())) in checkAnyInstHazards()
1220 if (!Use.isReg() || !TRI.isVGPR(MF.getRegInfo(), Use.getReg())) in checkMAIHazards()
1377 if (!Op.isReg() || !TRI.isVGPR(MF.getRegInfo(), Op.getReg())) in checkMAILdStHazards()
|
| /dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 211 bool isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const;
214 return isVGPR(MRI, Reg) || isAGPR(MRI, Reg); in isVectorRegister()
|
| H A D | GCNHazardRecognizer.cpp | 592 if (!Use.isReg() || TRI.isVGPR(MF.getRegInfo(), Use.getReg())) in checkVMEMHazards()
614 if (!Use.isReg() || !TRI->isVGPR(MF.getRegInfo(), Use.getReg())) in checkDPPHazards()
727 if (!TRI->isVGPR(MRI, Def.getReg())) in checkVALUHazardsHelper()
835 if (!Use.isReg() || TRI->isVGPR(MF.getRegInfo(), Use.getReg())) in checkAnyInstHazards()
1220 if (!Use.isReg() || !TRI.isVGPR(MF.getRegInfo(), Use.getReg())) in checkMAIHazards()
1377 if (!Op.isReg() || !TRI.isVGPR(MF.getRegInfo(), Op.getReg())) in checkMAILdStHazards()
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 212 bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const;
215 return isVGPR(MRI, Reg) || isAGPR(MRI, Reg); in isVectorRegister()
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 212 bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const;
215 return isVGPR(MRI, Reg) || isAGPR(MRI, Reg); in isVectorRegister()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 226 bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const;
229 return isVGPR(MRI, Reg) || isAGPR(MRI, Reg); in isVectorRegister()
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 219 bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const;
222 return isVGPR(MRI, Reg) || isAGPR(MRI, Reg); in isVectorRegister()
|
| H A D | GCNHazardRecognizer.cpp | 595 if (!Use.isReg() || TRI.isVGPR(MF.getRegInfo(), Use.getReg())) in checkVMEMHazards()
617 if (!Use.isReg() || !TRI->isVGPR(MF.getRegInfo(), Use.getReg())) in checkDPPHazards()
730 if (!TRI->isVGPR(MRI, Def.getReg())) in checkVALUHazardsHelper()
838 if (!Use.isReg() || TRI->isVGPR(MF.getRegInfo(), Use.getReg())) in checkAnyInstHazards()
1223 if (!Use.isReg() || !TRI.isVGPR(MF.getRegInfo(), Use.getReg())) in checkMAIHazards()
1380 if (!Op.isReg() || !TRI.isVGPR(MF.getRegInfo(), Op.getReg())) in checkMAILdStHazards()
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 229 bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const;
232 return isVGPR(MRI, Reg) || isAGPR(MRI, Reg); in isVectorRegister()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 229 bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const;
232 return isVGPR(MRI, Reg) || isAGPR(MRI, Reg); in isVectorRegister()
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 219 bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const;
222 return isVGPR(MRI, Reg) || isAGPR(MRI, Reg); in isVectorRegister()
|
| H A D | GCNHazardRecognizer.cpp | 595 if (!Use.isReg() || TRI.isVGPR(MF.getRegInfo(), Use.getReg())) in checkVMEMHazards()
617 if (!Use.isReg() || !TRI->isVGPR(MF.getRegInfo(), Use.getReg())) in checkDPPHazards()
730 if (!TRI->isVGPR(MRI, Def.getReg())) in checkVALUHazardsHelper()
838 if (!Use.isReg() || TRI->isVGPR(MF.getRegInfo(), Use.getReg())) in checkAnyInstHazards()
1223 if (!Use.isReg() || !TRI.isVGPR(MF.getRegInfo(), Use.getReg())) in checkMAIHazards()
1380 if (!Op.isReg() || !TRI.isVGPR(MF.getRegInfo(), Op.getReg())) in checkMAILdStHazards()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 229 bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const;
232 return isVGPR(MRI, Reg) || isAGPR(MRI, Reg); in isVectorRegister()
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 229 bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const;
232 return isVGPR(MRI, Reg) || isAGPR(MRI, Reg); in isVectorRegister()
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 229 bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const;
232 return isVGPR(MRI, Reg) || isAGPR(MRI, Reg); in isVectorRegister()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 246 bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const;
249 return isVGPR(MRI, Reg) || isAGPR(MRI, Reg); in isVectorRegister()
|