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Searched refs:ivl_logic_t (Results 1 – 6 of 6) sorted by relevance

/dports/cad/iverilog/verilog-11.0/tgt-sizer/
H A Dsizer_priv.h44 std::map<ivl_logic_t,unsigned> log_bytype;
H A Dsizer.cc188 for (map<ivl_logic_t,unsigned>::const_iterator cur = stats.log_bytype.begin() in show_stats()
239 for (map<ivl_logic_t,unsigned>::const_iterator cur = that.log_bytype.begin() in operator +=()
/dports/cad/iverilog/verilog-11.0/
H A Divl_target.h286 } ivl_logic_t; typedef
1098 extern ivl_logic_t ivl_logic_type(ivl_net_logic_t net);
H A Dt-dll.h526 ivl_logic_t type_;
H A Dt-dll-api.cc940 extern "C" ivl_logic_t ivl_logic_type(ivl_net_logic_t net) in ivl_logic_type()
/dports/cad/iverilog/verilog-11.0/tgt-vlog95/
H A Dlogic_lpm.c2386 ivl_logic_t logic_type = ivl_logic_type(nlogic); in dump_nexus_information()