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Searched refs:ivl_scope_tname (Results 1 – 13 of 13) sorted by relevance

/dports/cad/iverilog/verilog-11.0/tgt-vlog95/
H A Dscope.c267 (void) strcpy(name, ivl_scope_tname(scope)); in emit_mangled_name()
276 emit_id(ivl_scope_tname(scope)); in emit_mangled_name()
674 emit_id(ivl_scope_tname(scope)); in emit_named_block_scope()
681 emit_id(ivl_scope_tname(scope)); in emit_named_block_scope()
1052 ivl_scope_tname(scope)); in emit_scope()
1058 emit_id(ivl_scope_tname(scope)); in emit_scope()
1071 emit_id(ivl_scope_tname(scope)); in emit_scope()
1089 ivl_scope_tname(scope)); in emit_scope()
1113 ivl_scope_tname(scope)); in emit_scope()
1120 ivl_scope_tname(scope)); in emit_scope()
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/dports/cad/iverilog/verilog-11.0/tgt-vhdl/
H A Dstate.cc190 const char *tname = ivl_scope_tname(scope); in find_entity()
194 if (strcmp(tname, ivl_scope_tname((*it).first)) == 0) in find_entity()
250 if (strcmp(ivl_scope_tname(a), ivl_scope_tname(b)) != 0) in same_scope_type_name()
H A Dprocess.cc74 << ivl_scope_tname(scope) << " (" in generate_vhdl_process()
92 ivl_scope_tname(scope), ivl_process_file(proc), in draw_process()
H A Dscope.cc380 debug_msg("Declaring logic in scope type %s", ivl_scope_tname(scope)); in declare_logic()
644 debug_msg("Declaring signals in scope type %s", ivl_scope_tname(scope)); in declare_signals()
770 debug_msg("Generating function %s (%s)", ivl_scope_tname(scope), in draw_function()
777 const char *funcname = ivl_scope_tname(scope); in draw_function()
878 const char *taskname = ivl_scope_tname(scope); in draw_task()
919 const string tname = valid_entity_name(ivl_scope_tname(scope)); in create_skeleton_entity_for()
934 ss << "Generated from Verilog module " << ivl_scope_tname(scope) in create_skeleton_entity_for()
980 ivl_scope_tname(scope), depth); in draw_skeleton_scope()
H A Dexpr.cc554 const char *funcname = ivl_scope_tname(defscope); in translate_ufunc()
/dports/cad/iverilog/verilog-11.0/tgt-stub/
H A Dstub.c1707 fprintf(out, " module %s%s", ivl_scope_tname(net), in show_scope()
1711 fprintf(out, " function %s%s", is_auto, ivl_scope_tname(net)); in show_scope()
1714 fprintf(out, " begin : %s", ivl_scope_tname(net)); in show_scope()
1717 fprintf(out, " fork : %s", ivl_scope_tname(net)); in show_scope()
1720 fprintf(out, " task %s%s", is_auto, ivl_scope_tname(net)); in show_scope()
1723 fprintf(out, " class %s", ivl_scope_tname(net)); in show_scope()
1727 ivl_scope_tname(net)); in show_scope()
/dports/cad/iverilog/verilog-11.0/
H A Divl.def243 ivl_scope_tname
H A Divl_target.h1897 extern const char* ivl_scope_tname(ivl_scope_t net);
H A Dcppcheck.sup433 //ivl_scope_tname()
H A Dt-dll-api.cc2368 extern "C" const char* ivl_scope_tname(ivl_scope_t net) in ivl_scope_tname() function
/dports/cad/iverilog/verilog-11.0/tgt-pcb/
H A Dscope.cc125 printf(" Component %s is %s\n", ivl_scope_name(scope), ivl_scope_tname(scope)); in black_box()
/dports/cad/iverilog/verilog-11.0/tgt-fpga/
H A Dedif.c217 cur = edif_xlibrary_findcell(xlib, ivl_scope_tname(scope)); in edif_xlibrary_scope_cell()
231 cur = edif_xcell_create(xlib, ivl_scope_tname(scope), port_count); in edif_xlibrary_scope_cell()
/dports/cad/iverilog/verilog-11.0/tgt-vvp/
H A Dvvp_scope.c2320 vvp_mangle_name(ivl_scope_tname(net)), in draw_scope()