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Searched refs:ixCG_SPLL_FUNC_CNTL_2 (Results 1 – 25 of 30) sorted by relevance

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/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dfiji_baco.c64 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
68 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
73 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
H A Dci_baco.c66 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
70 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
75 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
H A Dtonga_baco.c64 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
68 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
73 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dfiji_baco.c64 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
68 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
73 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
H A Dci_baco.c66 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
70 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
75 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
H A Dtonga_baco.c64 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
68 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
73 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dfiji_baco.c64 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
68 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
73 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
H A Dci_baco.c66 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
70 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
75 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
H A Dtonga_baco.c64 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
68 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
73 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_7_0_0_d.h46 #define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 macro
H A Dsmu_7_1_1_d.h46 #define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 macro
H A Dsmu_7_1_2_d.h46 #define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 macro
H A Dsmu_7_1_3_d.h49 #define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 macro
H A Dsmu_7_0_1_d.h46 #define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 macro
H A Dsmu_7_1_0_d.h46 #define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_7_0_0_d.h46 #define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 macro
H A Dsmu_7_1_1_d.h46 #define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 macro
H A Dsmu_7_1_2_d.h46 #define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 macro
H A Dsmu_7_1_3_d.h49 #define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 macro
H A Dsmu_7_0_1_d.h46 #define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_7_0_0_d.h46 #define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 macro
H A Dsmu_7_1_1_d.h46 #define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 macro
H A Dsmu_7_1_2_d.h46 #define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 macro
H A Dsmu_7_1_3_d.h49 #define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 macro
H A Dsmu_7_0_1_d.h46 #define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 macro

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