| /dports/sysutils/u-boot-chip/u-boot-2021.07/board/gdsys/common/ |
| H A D | dp501.c | 56 u8 lane_cnt; in dp501_link_training() local
70 lane_cnt = 4; in dp501_link_training()
72 lane_cnt = max_lane_cnt; in dp501_link_training()
73 if (lane_cnt != max_lane_cnt) in dp501_link_training()
75 max_lane_cnt, lane_cnt); in dp501_link_training()
76 i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */ in dp501_link_training()
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/board/gdsys/common/ |
| H A D | dp501.c | 54 u8 lane_cnt; in dp501_link_training() local
68 lane_cnt = 4; in dp501_link_training()
70 lane_cnt = max_lane_cnt; in dp501_link_training()
71 if (lane_cnt != max_lane_cnt) in dp501_link_training()
73 max_lane_cnt, lane_cnt); in dp501_link_training()
74 i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */ in dp501_link_training()
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/board/gdsys/common/ |
| H A D | dp501.c | 54 u8 lane_cnt; in dp501_link_training() local
68 lane_cnt = 4; in dp501_link_training()
70 lane_cnt = max_lane_cnt; in dp501_link_training()
71 if (lane_cnt != max_lane_cnt) in dp501_link_training()
73 max_lane_cnt, lane_cnt); in dp501_link_training()
74 i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */ in dp501_link_training()
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/board/gdsys/common/ |
| H A D | dp501.c | 56 u8 lane_cnt; in dp501_link_training() local
70 lane_cnt = 4; in dp501_link_training()
72 lane_cnt = max_lane_cnt; in dp501_link_training()
73 if (lane_cnt != max_lane_cnt) in dp501_link_training()
75 max_lane_cnt, lane_cnt); in dp501_link_training()
76 i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */ in dp501_link_training()
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/board/gdsys/common/ |
| H A D | dp501.c | 56 u8 lane_cnt; in dp501_link_training() local
70 lane_cnt = 4; in dp501_link_training()
72 lane_cnt = max_lane_cnt; in dp501_link_training()
73 if (lane_cnt != max_lane_cnt) in dp501_link_training()
75 max_lane_cnt, lane_cnt); in dp501_link_training()
76 i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */ in dp501_link_training()
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/board/gdsys/common/ |
| H A D | dp501.c | 56 u8 lane_cnt; in dp501_link_training() local
70 lane_cnt = 4; in dp501_link_training()
72 lane_cnt = max_lane_cnt; in dp501_link_training()
73 if (lane_cnt != max_lane_cnt) in dp501_link_training()
75 max_lane_cnt, lane_cnt); in dp501_link_training()
76 i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */ in dp501_link_training()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/board/gdsys/common/ |
| H A D | dp501.c | 56 u8 lane_cnt; in dp501_link_training() local
70 lane_cnt = 4; in dp501_link_training()
72 lane_cnt = max_lane_cnt; in dp501_link_training()
73 if (lane_cnt != max_lane_cnt) in dp501_link_training()
75 max_lane_cnt, lane_cnt); in dp501_link_training()
76 i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */ in dp501_link_training()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/board/gdsys/common/ |
| H A D | dp501.c | 56 u8 lane_cnt; in dp501_link_training() local
70 lane_cnt = 4; in dp501_link_training()
72 lane_cnt = max_lane_cnt; in dp501_link_training()
73 if (lane_cnt != max_lane_cnt) in dp501_link_training()
75 max_lane_cnt, lane_cnt); in dp501_link_training()
76 i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */ in dp501_link_training()
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/board/gdsys/common/ |
| H A D | dp501.c | 56 u8 lane_cnt; in dp501_link_training() local
70 lane_cnt = 4; in dp501_link_training()
72 lane_cnt = max_lane_cnt; in dp501_link_training()
73 if (lane_cnt != max_lane_cnt) in dp501_link_training()
75 max_lane_cnt, lane_cnt); in dp501_link_training()
76 i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */ in dp501_link_training()
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/board/gdsys/common/ |
| H A D | dp501.c | 56 u8 lane_cnt; in dp501_link_training() local
70 lane_cnt = 4; in dp501_link_training()
72 lane_cnt = max_lane_cnt; in dp501_link_training()
73 if (lane_cnt != max_lane_cnt) in dp501_link_training()
75 max_lane_cnt, lane_cnt); in dp501_link_training()
76 i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */ in dp501_link_training()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/board/gdsys/common/ |
| H A D | dp501.c | 56 u8 lane_cnt; in dp501_link_training() local
70 lane_cnt = 4; in dp501_link_training()
72 lane_cnt = max_lane_cnt; in dp501_link_training()
73 if (lane_cnt != max_lane_cnt) in dp501_link_training()
75 max_lane_cnt, lane_cnt); in dp501_link_training()
76 i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */ in dp501_link_training()
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/board/gdsys/common/ |
| H A D | dp501.c | 56 u8 lane_cnt; in dp501_link_training() local
70 lane_cnt = 4; in dp501_link_training()
72 lane_cnt = max_lane_cnt; in dp501_link_training()
73 if (lane_cnt != max_lane_cnt) in dp501_link_training()
75 max_lane_cnt, lane_cnt); in dp501_link_training()
76 i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */ in dp501_link_training()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/board/gdsys/common/ |
| H A D | dp501.c | 56 u8 lane_cnt; in dp501_link_training() local
70 lane_cnt = 4; in dp501_link_training()
72 lane_cnt = max_lane_cnt; in dp501_link_training()
73 if (lane_cnt != max_lane_cnt) in dp501_link_training()
75 max_lane_cnt, lane_cnt); in dp501_link_training()
76 i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */ in dp501_link_training()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/board/gdsys/common/ |
| H A D | dp501.c | 56 u8 lane_cnt; in dp501_link_training() local
70 lane_cnt = 4; in dp501_link_training()
72 lane_cnt = max_lane_cnt; in dp501_link_training()
73 if (lane_cnt != max_lane_cnt) in dp501_link_training()
75 max_lane_cnt, lane_cnt); in dp501_link_training()
76 i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */ in dp501_link_training()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/board/gdsys/common/ |
| H A D | dp501.c | 56 u8 lane_cnt; in dp501_link_training() local
70 lane_cnt = 4; in dp501_link_training()
72 lane_cnt = max_lane_cnt; in dp501_link_training()
73 if (lane_cnt != max_lane_cnt) in dp501_link_training()
75 max_lane_cnt, lane_cnt); in dp501_link_training()
76 i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */ in dp501_link_training()
|
| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/board/gdsys/common/ |
| H A D | dp501.c | 56 u8 lane_cnt; in dp501_link_training() local
70 lane_cnt = 4; in dp501_link_training()
72 lane_cnt = max_lane_cnt; in dp501_link_training()
73 if (lane_cnt != max_lane_cnt) in dp501_link_training()
75 max_lane_cnt, lane_cnt); in dp501_link_training()
76 i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */ in dp501_link_training()
|
| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/board/gdsys/common/ |
| H A D | dp501.c | 56 u8 lane_cnt; in dp501_link_training() local
70 lane_cnt = 4; in dp501_link_training()
72 lane_cnt = max_lane_cnt; in dp501_link_training()
73 if (lane_cnt != max_lane_cnt) in dp501_link_training()
75 max_lane_cnt, lane_cnt); in dp501_link_training()
76 i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */ in dp501_link_training()
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/board/gdsys/common/ |
| H A D | dp501.c | 56 u8 lane_cnt; in dp501_link_training() local
70 lane_cnt = 4; in dp501_link_training()
72 lane_cnt = max_lane_cnt; in dp501_link_training()
73 if (lane_cnt != max_lane_cnt) in dp501_link_training()
75 max_lane_cnt, lane_cnt); in dp501_link_training()
76 i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */ in dp501_link_training()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/board/gdsys/common/ |
| H A D | dp501.c | 56 u8 lane_cnt; in dp501_link_training() local
70 lane_cnt = 4; in dp501_link_training()
72 lane_cnt = max_lane_cnt; in dp501_link_training()
73 if (lane_cnt != max_lane_cnt) in dp501_link_training()
75 max_lane_cnt, lane_cnt); in dp501_link_training()
76 i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */ in dp501_link_training()
|
| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/board/gdsys/common/ |
| H A D | dp501.c | 56 u8 lane_cnt; in dp501_link_training() local
70 lane_cnt = 4; in dp501_link_training()
72 lane_cnt = max_lane_cnt; in dp501_link_training()
73 if (lane_cnt != max_lane_cnt) in dp501_link_training()
75 max_lane_cnt, lane_cnt); in dp501_link_training()
76 i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */ in dp501_link_training()
|
| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/board/gdsys/common/ |
| H A D | dp501.c | 56 u8 lane_cnt; in dp501_link_training() local
70 lane_cnt = 4; in dp501_link_training()
72 lane_cnt = max_lane_cnt; in dp501_link_training()
73 if (lane_cnt != max_lane_cnt) in dp501_link_training()
75 max_lane_cnt, lane_cnt); in dp501_link_training()
76 i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */ in dp501_link_training()
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/board/gdsys/common/ |
| H A D | dp501.c | 56 u8 lane_cnt; in dp501_link_training() local
70 lane_cnt = 4; in dp501_link_training()
72 lane_cnt = max_lane_cnt; in dp501_link_training()
73 if (lane_cnt != max_lane_cnt) in dp501_link_training()
75 max_lane_cnt, lane_cnt); in dp501_link_training()
76 i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */ in dp501_link_training()
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/board/gdsys/common/ |
| H A D | dp501.c | 54 u8 lane_cnt; in dp501_link_training() local
68 lane_cnt = 4; in dp501_link_training()
70 lane_cnt = max_lane_cnt; in dp501_link_training()
71 if (lane_cnt != max_lane_cnt) in dp501_link_training()
73 max_lane_cnt, lane_cnt); in dp501_link_training()
74 i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */ in dp501_link_training()
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/board/gdsys/common/ |
| H A D | dp501.c | 54 u8 lane_cnt; in dp501_link_training() local
68 lane_cnt = 4; in dp501_link_training()
70 lane_cnt = max_lane_cnt; in dp501_link_training()
71 if (lane_cnt != max_lane_cnt) in dp501_link_training()
73 max_lane_cnt, lane_cnt); in dp501_link_training()
74 i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */ in dp501_link_training()
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/board/gdsys/common/ |
| H A D | dp501.c | 56 u8 lane_cnt; in dp501_link_training() local
70 lane_cnt = 4; in dp501_link_training()
72 lane_cnt = max_lane_cnt; in dp501_link_training()
73 if (lane_cnt != max_lane_cnt) in dp501_link_training()
75 max_lane_cnt, lane_cnt); in dp501_link_training()
76 i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */ in dp501_link_training()
|