/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/PowerPC/ |
H A D | variable_elem_vec_extracts.ll | 18 ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 31 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 52 ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 60 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 75 ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 82 ; CHECK-BE: lvsl [[SHMSKREG:[0-9]+]], 0, [[ELNOREG]] 98 ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 104 ; CHECK-P7-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 110 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]]
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/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/PowerPC/ |
H A D | variable_elem_vec_extracts.ll | 18 ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 31 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 52 ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 60 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 75 ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 82 ; CHECK-BE: lvsl [[SHMSKREG:[0-9]+]], 0, [[ELNOREG]] 98 ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 104 ; CHECK-P7-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 110 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/PowerPC/ |
H A D | variable_elem_vec_extracts.ll | 18 ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 31 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 52 ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 60 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 75 ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 82 ; CHECK-BE: lvsl [[SHMSKREG:[0-9]+]], 0, [[ELNOREG]] 98 ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 104 ; CHECK-P7-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 110 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]]
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/PowerPC/ |
H A D | variable_elem_vec_extracts.ll | 18 ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 31 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 52 ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 60 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 75 ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 82 ; CHECK-BE: lvsl [[SHMSKREG:[0-9]+]], 0, [[ELNOREG]] 98 ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 104 ; CHECK-P7-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 110 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]]
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/PowerPC/ |
H A D | variable_elem_vec_extracts.ll | 18 ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 31 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 52 ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 60 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 75 ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 82 ; CHECK-BE: lvsl [[SHMSKREG:[0-9]+]], 0, [[ELNOREG]] 98 ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 104 ; CHECK-P7-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 110 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]]
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/PowerPC/ |
H A D | variable_elem_vec_extracts.ll | 18 ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 31 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 52 ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 60 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 75 ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 82 ; CHECK-BE: lvsl [[SHMSKREG:[0-9]+]], 0, [[ELNOREG]] 98 ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 104 ; CHECK-P7-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 110 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]]
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/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/PowerPC/ |
H A D | variable_elem_vec_extracts.ll | 18 ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 31 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 52 ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 60 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 75 ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 82 ; CHECK-BE: lvsl [[SHMSKREG:[0-9]+]], 0, [[ELNOREG]] 98 ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 104 ; CHECK-P7-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 110 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]]
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/PowerPC/ |
H A D | variable_elem_vec_extracts.ll | 18 ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 31 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 52 ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 60 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 75 ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 82 ; CHECK-BE: lvsl [[SHMSKREG:[0-9]+]], 0, [[ELNOREG]] 98 ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 104 ; CHECK-P7-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 110 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]]
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/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/PowerPC/ |
H A D | variable_elem_vec_extracts.ll | 18 ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 31 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 52 ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 60 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 75 ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 82 ; CHECK-BE: lvsl [[SHMSKREG:[0-9]+]], 0, [[ELNOREG]] 98 ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 104 ; CHECK-P7-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 110 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]]
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/PowerPC/ |
H A D | variable_elem_vec_extracts.ll | 18 ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 31 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 52 ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 60 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 75 ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 82 ; CHECK-BE: lvsl [[SHMSKREG:[0-9]+]], 0, [[ELNOREG]] 98 ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 104 ; CHECK-P7-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 110 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]]
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/PowerPC/ |
H A D | variable_elem_vec_extracts.ll | 18 ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 31 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 52 ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 60 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 75 ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 82 ; CHECK-BE: lvsl [[SHMSKREG:[0-9]+]], 0, [[ELNOREG]] 98 ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 104 ; CHECK-P7-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 110 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]]
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/PowerPC/ |
H A D | variable_elem_vec_extracts.ll | 18 ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 31 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 52 ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 60 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 75 ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 82 ; CHECK-BE: lvsl [[SHMSKREG:[0-9]+]], 0, [[ELNOREG]] 98 ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 104 ; CHECK-P7-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 110 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]]
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/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/PowerPC/ |
H A D | variable_elem_vec_extracts.ll | 18 ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 31 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 52 ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 60 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 75 ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 82 ; CHECK-BE: lvsl [[SHMSKREG:[0-9]+]], 0, [[ELNOREG]] 98 ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 104 ; CHECK-P7-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 110 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]]
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/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/PowerPC/ |
H A D | variable_elem_vec_extracts.ll | 18 ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 31 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 52 ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 60 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 75 ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 82 ; CHECK-BE: lvsl [[SHMSKREG:[0-9]+]], 0, [[ELNOREG]] 98 ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 104 ; CHECK-P7-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 110 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]]
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/PowerPC/ |
H A D | variable_elem_vec_extracts.ll | 18 ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 31 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 52 ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 60 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 75 ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 82 ; CHECK-BE: lvsl [[SHMSKREG:[0-9]+]], 0, [[ELNOREG]] 98 ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 104 ; CHECK-P7-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 110 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]]
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/dports/devel/liboil/liboil-0.3.17/liboil/powerpc_asm_blocks/ |
H A D | recon8x8_altivec.c | 191 lvsl v8,r4,r7 //load alignment vector for refs in recon8x8_inter_altivec() 203 lvsl v8,r4,r7 //load alignment vector for refs in recon8x8_inter_altivec() 212 lvsl v8,r4,r7 //load alignment vector for refs in recon8x8_inter_altivec() 221 lvsl v8,r4,r7 //load alignment vector for refs in recon8x8_inter_altivec() 230 lvsl v8,r4,r7 //load alignment vector for refs in recon8x8_inter_altivec() 239 lvsl v8,r4,r7 //load alignment vector for refs in recon8x8_inter_altivec() 248 lvsl v8,r4,r7 //load alignment vector for refs in recon8x8_inter_altivec() 257 lvsl v8,r4,r7 //load alignment vector for refs in recon8x8_inter_altivec() 409 lvsl v8,r4,r8 //load alignment vector for RefPtr1 in recon8x8_inter2_altivec() 421 lvsl v8,r4,r8 //load alignment vector for RefPtr1 in recon8x8_inter2_altivec() [all …]
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/dports/www/node10/node-v10.24.1/deps/openssl/config/archs/aix-gcc/asm/crypto/aes/ |
H A D | aesp8-ppc.s | 345 lvsl 2,0,3 347 lvsl 3,0,11 352 lvsl 5,0,5 412 lvsl 2,0,3 414 lvsl 3,0,11 419 lvsl 5,0,5 483 lvsl 6,0,7 489 lvsl 10,0,6 611 lvsl 8,0,8 1217 lvsl 6,0,7 [all …]
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H A D | vpaes-ppc.s | 267 lvsl 27, 0, 3 271 lvsl 31, 0, 5 499 lvsl 27, 0, 3 503 lvsl 31, 0, 5 609 lvsl 27, 0, 31 616 lvsl 31, 0, 5 740 lvsl 29, 0, 8 892 lvsl 29, 0, 0
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/dports/www/node10/node-v10.24.1/deps/openssl/config/archs/aix-gcc/asm_avx2/crypto/aes/ |
H A D | aesp8-ppc.s | 345 lvsl 2,0,3 347 lvsl 3,0,11 352 lvsl 5,0,5 412 lvsl 2,0,3 414 lvsl 3,0,11 419 lvsl 5,0,5 483 lvsl 6,0,7 489 lvsl 10,0,6 611 lvsl 8,0,8 1217 lvsl 6,0,7 [all …]
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/dports/www/node10/node-v10.24.1/deps/openssl/config/archs/linux-ppc/asm_avx2/crypto/aes/ |
H A D | aesp8-ppc.s | 348 lvsl 2,0,3 350 lvsl 3,0,11 355 lvsl 5,0,5 416 lvsl 2,0,3 418 lvsl 3,0,11 423 lvsl 5,0,5 488 lvsl 6,0,7 494 lvsl 10,0,6 616 lvsl 8,0,8 1223 lvsl 6,0,7 [all …]
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/dports/www/node10/node-v10.24.1/deps/openssl/config/archs/linux-ppc/asm/crypto/aes/ |
H A D | aesp8-ppc.s | 348 lvsl 2,0,3 350 lvsl 3,0,11 355 lvsl 5,0,5 416 lvsl 2,0,3 418 lvsl 3,0,11 423 lvsl 5,0,5 488 lvsl 6,0,7 494 lvsl 10,0,6 616 lvsl 8,0,8 1223 lvsl 6,0,7 [all …]
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/dports/www/node10/node-v10.24.1/deps/openssl/config/archs/linux-ppc64/asm/crypto/aes/ |
H A D | aesp8-ppc.s | 365 lvsl 2,0,3 367 lvsl 3,0,11 372 lvsl 5,0,5 439 lvsl 2,0,3 441 lvsl 3,0,11 446 lvsl 5,0,5 517 lvsl 6,0,7 523 lvsl 10,0,6 645 lvsl 8,0,8 1258 lvsl 6,0,7 [all …]
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/dports/www/node10/node-v10.24.1/deps/openssl/config/archs/linux-ppc64/asm_avx2/crypto/aes/ |
H A D | aesp8-ppc.s | 365 lvsl 2,0,3 367 lvsl 3,0,11 372 lvsl 5,0,5 439 lvsl 2,0,3 441 lvsl 3,0,11 446 lvsl 5,0,5 517 lvsl 6,0,7 523 lvsl 10,0,6 645 lvsl 8,0,8 1258 lvsl 6,0,7 [all …]
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/dports/www/node10/node-v10.24.1/deps/openssl/config/archs/aix64-gcc/asm_avx2/crypto/aes/ |
H A D | aesp8-ppc.s | 345 lvsl 2,0,3 347 lvsl 3,0,11 352 lvsl 5,0,5 412 lvsl 2,0,3 414 lvsl 3,0,11 419 lvsl 5,0,5 483 lvsl 6,0,7 489 lvsl 10,0,6 611 lvsl 8,0,8 1217 lvsl 6,0,7 [all …]
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/dports/www/node10/node-v10.24.1/deps/openssl/config/archs/aix64-gcc/asm/crypto/aes/ |
H A D | aesp8-ppc.s | 345 lvsl 2,0,3 347 lvsl 3,0,11 352 lvsl 5,0,5 412 lvsl 2,0,3 414 lvsl 3,0,11 419 lvsl 5,0,5 483 lvsl 6,0,7 489 lvsl 10,0,6 611 lvsl 8,0,8 1217 lvsl 6,0,7 [all …]
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