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/dports/lang/gcc11/gcc-11.2.0/gcc/testsuite/gcc.target/msp430/
H A Doperand-modifiers.c21 volatile unsigned long long mem64 = MEM64_VAL; variable
79 __asm__("mov %A1, %0\n" : "=m" (word0) : "m" (mem64)); in main()
80 __asm__("mov %B1, %0\n" : "=m" (word1) : "m" (mem64)); in main()
81 __asm__("mov %C1, %0\n" : "=m" (word2) : "m" (mem64)); in main()
82 __asm__("mov %D1, %0\n" : "=m" (word3) : "m" (mem64)); in main()
93 __asm__("mov.b %A1, %0\n" : "=m" (byte0) : "m" (mem64)); in main()
94 __asm__("mov.b %d1, %0\n" : "=m" (byte1) : "m" (mem64)); in main()
95 __asm__("mov.b %B1, %0\n" : "=m" (byte2) : "m" (mem64)); in main()
96 __asm__("mov.b %e1, %0\n" : "=m" (byte3) : "m" (mem64)); in main()
97 __asm__("mov.b %C1, %0\n" : "=m" (byte4) : "m" (mem64)); in main()
[all …]
/dports/lang/gcc11-devel/gcc-11-20211009/gcc/testsuite/gcc.target/msp430/
H A Doperand-modifiers.c21 volatile unsigned long long mem64 = MEM64_VAL; variable
79 __asm__("mov %A1, %0\n" : "=m" (word0) : "m" (mem64)); in main()
80 __asm__("mov %B1, %0\n" : "=m" (word1) : "m" (mem64)); in main()
81 __asm__("mov %C1, %0\n" : "=m" (word2) : "m" (mem64)); in main()
82 __asm__("mov %D1, %0\n" : "=m" (word3) : "m" (mem64)); in main()
93 __asm__("mov.b %A1, %0\n" : "=m" (byte0) : "m" (mem64)); in main()
94 __asm__("mov.b %d1, %0\n" : "=m" (byte1) : "m" (mem64)); in main()
95 __asm__("mov.b %B1, %0\n" : "=m" (byte2) : "m" (mem64)); in main()
96 __asm__("mov.b %e1, %0\n" : "=m" (byte3) : "m" (mem64)); in main()
97 __asm__("mov.b %C1, %0\n" : "=m" (byte4) : "m" (mem64)); in main()
[all …]
/dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/testsuite/gcc.target/msp430/
H A Doperand-modifiers.c21 volatile unsigned long long mem64 = MEM64_VAL; variable
79 __asm__("mov %A1, %0\n" : "=m" (word0) : "m" (mem64)); in main()
80 __asm__("mov %B1, %0\n" : "=m" (word1) : "m" (mem64)); in main()
81 __asm__("mov %C1, %0\n" : "=m" (word2) : "m" (mem64)); in main()
82 __asm__("mov %D1, %0\n" : "=m" (word3) : "m" (mem64)); in main()
93 __asm__("mov.b %A1, %0\n" : "=m" (byte0) : "m" (mem64)); in main()
94 __asm__("mov.b %d1, %0\n" : "=m" (byte1) : "m" (mem64)); in main()
95 __asm__("mov.b %B1, %0\n" : "=m" (byte2) : "m" (mem64)); in main()
96 __asm__("mov.b %e1, %0\n" : "=m" (byte3) : "m" (mem64)); in main()
97 __asm__("mov.b %C1, %0\n" : "=m" (byte4) : "m" (mem64)); in main()
[all …]
/dports/lang/gcc12-devel/gcc-12-20211205/gcc/testsuite/gcc.target/msp430/
H A Doperand-modifiers.c21 volatile unsigned long long mem64 = MEM64_VAL; variable
79 __asm__("mov %A1, %0\n" : "=m" (word0) : "m" (mem64)); in main()
80 __asm__("mov %B1, %0\n" : "=m" (word1) : "m" (mem64)); in main()
81 __asm__("mov %C1, %0\n" : "=m" (word2) : "m" (mem64)); in main()
82 __asm__("mov %D1, %0\n" : "=m" (word3) : "m" (mem64)); in main()
93 __asm__("mov.b %A1, %0\n" : "=m" (byte0) : "m" (mem64)); in main()
94 __asm__("mov.b %d1, %0\n" : "=m" (byte1) : "m" (mem64)); in main()
95 __asm__("mov.b %B1, %0\n" : "=m" (byte2) : "m" (mem64)); in main()
96 __asm__("mov.b %e1, %0\n" : "=m" (byte3) : "m" (mem64)); in main()
97 __asm__("mov.b %C1, %0\n" : "=m" (byte4) : "m" (mem64)); in main()
[all …]
/dports/security/liboqs/liboqs-0.7.0/src/kem/classic_mceliece/pqclean_mceliece8192128f_avx/
H A Dupdate_asm.S54 # qhasm: s0 = mem64[ input_0 + 0 ]
59 # qhasm: s1 = mem64[ input_0 + 8 ]
79 # qhasm: mem64[ input_0 + 0 ] = s0
84 # qhasm: mem64[ input_0 + 8 ] = s1
94 # qhasm: s0 = mem64[ input_0 + 0 ]
99 # qhasm: s1 = mem64[ input_0 + 8 ]
119 # qhasm: mem64[ input_0 + 0 ] = s0
124 # qhasm: mem64[ input_0 + 8 ] = s1
134 # qhasm: s0 = mem64[ input_0 + 0 ]
139 # qhasm: s1 = mem64[ input_0 + 8 ]
[all …]
H A Dvec_reduce_asm.S56 # qhasm: t0 = mem64[ input_0 + 192 ]
61 # qhasm: t1 = mem64[ input_0 + 200 ]
91 # qhasm: t0 = mem64[ input_0 + 176 ]
96 # qhasm: t1 = mem64[ input_0 + 184 ]
126 # qhasm: t0 = mem64[ input_0 + 160 ]
131 # qhasm: t1 = mem64[ input_0 + 168 ]
161 # qhasm: t0 = mem64[ input_0 + 144 ]
166 # qhasm: t1 = mem64[ input_0 + 152 ]
266 # qhasm: t0 = mem64[ input_0 + 96 ]
476 # qhasm: t0 = mem64[ input_0 + 0 ]
[all …]
/dports/security/liboqs/liboqs-0.7.0/src/kem/classic_mceliece/pqclean_mceliece6688128_avx/
H A Dupdate_asm.S54 # qhasm: s0 = mem64[ input_0 + 0 ]
59 # qhasm: s1 = mem64[ input_0 + 8 ]
79 # qhasm: mem64[ input_0 + 0 ] = s0
84 # qhasm: mem64[ input_0 + 8 ] = s1
94 # qhasm: s0 = mem64[ input_0 + 0 ]
99 # qhasm: s1 = mem64[ input_0 + 8 ]
119 # qhasm: mem64[ input_0 + 0 ] = s0
124 # qhasm: mem64[ input_0 + 8 ] = s1
134 # qhasm: s0 = mem64[ input_0 + 0 ]
139 # qhasm: s1 = mem64[ input_0 + 8 ]
[all …]
H A Dvec_reduce_asm.S56 # qhasm: t0 = mem64[ input_0 + 192 ]
61 # qhasm: t1 = mem64[ input_0 + 200 ]
91 # qhasm: t0 = mem64[ input_0 + 176 ]
96 # qhasm: t1 = mem64[ input_0 + 184 ]
126 # qhasm: t0 = mem64[ input_0 + 160 ]
131 # qhasm: t1 = mem64[ input_0 + 168 ]
161 # qhasm: t0 = mem64[ input_0 + 144 ]
166 # qhasm: t1 = mem64[ input_0 + 152 ]
266 # qhasm: t0 = mem64[ input_0 + 96 ]
476 # qhasm: t0 = mem64[ input_0 + 0 ]
[all …]
/dports/security/liboqs/liboqs-0.7.0/src/kem/classic_mceliece/pqclean_mceliece6960119f_avx/
H A Dupdate_asm.S54 # qhasm: s0 = mem64[ input_0 + 0 ]
59 # qhasm: s1 = mem64[ input_0 + 8 ]
79 # qhasm: mem64[ input_0 + 0 ] = s0
84 # qhasm: mem64[ input_0 + 8 ] = s1
94 # qhasm: s0 = mem64[ input_0 + 0 ]
99 # qhasm: s1 = mem64[ input_0 + 8 ]
119 # qhasm: mem64[ input_0 + 0 ] = s0
124 # qhasm: mem64[ input_0 + 8 ] = s1
134 # qhasm: s0 = mem64[ input_0 + 0 ]
139 # qhasm: s1 = mem64[ input_0 + 8 ]
[all …]
H A Dvec_reduce_asm.S56 # qhasm: t0 = mem64[ input_0 + 192 ]
61 # qhasm: t1 = mem64[ input_0 + 200 ]
91 # qhasm: t0 = mem64[ input_0 + 176 ]
96 # qhasm: t1 = mem64[ input_0 + 184 ]
126 # qhasm: t0 = mem64[ input_0 + 160 ]
131 # qhasm: t1 = mem64[ input_0 + 168 ]
161 # qhasm: t0 = mem64[ input_0 + 144 ]
166 # qhasm: t1 = mem64[ input_0 + 152 ]
266 # qhasm: t0 = mem64[ input_0 + 96 ]
476 # qhasm: t0 = mem64[ input_0 + 0 ]
[all …]
/dports/security/liboqs/liboqs-0.7.0/src/kem/classic_mceliece/pqclean_mceliece8192128_avx/
H A Dupdate_asm.S54 # qhasm: s0 = mem64[ input_0 + 0 ]
59 # qhasm: s1 = mem64[ input_0 + 8 ]
79 # qhasm: mem64[ input_0 + 0 ] = s0
84 # qhasm: mem64[ input_0 + 8 ] = s1
94 # qhasm: s0 = mem64[ input_0 + 0 ]
99 # qhasm: s1 = mem64[ input_0 + 8 ]
119 # qhasm: mem64[ input_0 + 0 ] = s0
124 # qhasm: mem64[ input_0 + 8 ] = s1
134 # qhasm: s0 = mem64[ input_0 + 0 ]
139 # qhasm: s1 = mem64[ input_0 + 8 ]
[all …]
H A Dvec_reduce_asm.S56 # qhasm: t0 = mem64[ input_0 + 192 ]
61 # qhasm: t1 = mem64[ input_0 + 200 ]
91 # qhasm: t0 = mem64[ input_0 + 176 ]
96 # qhasm: t1 = mem64[ input_0 + 184 ]
126 # qhasm: t0 = mem64[ input_0 + 160 ]
131 # qhasm: t1 = mem64[ input_0 + 168 ]
161 # qhasm: t0 = mem64[ input_0 + 144 ]
166 # qhasm: t1 = mem64[ input_0 + 152 ]
266 # qhasm: t0 = mem64[ input_0 + 96 ]
476 # qhasm: t0 = mem64[ input_0 + 0 ]
[all …]
/dports/security/liboqs/liboqs-0.7.0/src/kem/classic_mceliece/pqclean_mceliece460896f_avx/
H A Dupdate_asm.S54 # qhasm: s0 = mem64[ input_0 + 0 ]
59 # qhasm: s1 = mem64[ input_0 + 8 ]
79 # qhasm: mem64[ input_0 + 0 ] = s0
84 # qhasm: mem64[ input_0 + 8 ] = s1
94 # qhasm: s0 = mem64[ input_0 + 0 ]
99 # qhasm: s1 = mem64[ input_0 + 8 ]
119 # qhasm: mem64[ input_0 + 0 ] = s0
124 # qhasm: mem64[ input_0 + 8 ] = s1
134 # qhasm: s0 = mem64[ input_0 + 0 ]
139 # qhasm: s1 = mem64[ input_0 + 8 ]
[all …]
H A Dvec_reduce_asm.S56 # qhasm: t0 = mem64[ input_0 + 192 ]
61 # qhasm: t1 = mem64[ input_0 + 200 ]
91 # qhasm: t0 = mem64[ input_0 + 176 ]
96 # qhasm: t1 = mem64[ input_0 + 184 ]
126 # qhasm: t0 = mem64[ input_0 + 160 ]
131 # qhasm: t1 = mem64[ input_0 + 168 ]
161 # qhasm: t0 = mem64[ input_0 + 144 ]
166 # qhasm: t1 = mem64[ input_0 + 152 ]
266 # qhasm: t0 = mem64[ input_0 + 96 ]
476 # qhasm: t0 = mem64[ input_0 + 0 ]
[all …]
/dports/security/liboqs/liboqs-0.7.0/src/kem/classic_mceliece/pqclean_mceliece6688128f_avx/
H A Dupdate_asm.S54 # qhasm: s0 = mem64[ input_0 + 0 ]
59 # qhasm: s1 = mem64[ input_0 + 8 ]
79 # qhasm: mem64[ input_0 + 0 ] = s0
84 # qhasm: mem64[ input_0 + 8 ] = s1
94 # qhasm: s0 = mem64[ input_0 + 0 ]
99 # qhasm: s1 = mem64[ input_0 + 8 ]
119 # qhasm: mem64[ input_0 + 0 ] = s0
124 # qhasm: mem64[ input_0 + 8 ] = s1
134 # qhasm: s0 = mem64[ input_0 + 0 ]
139 # qhasm: s1 = mem64[ input_0 + 8 ]
[all …]
H A Dvec_reduce_asm.S56 # qhasm: t0 = mem64[ input_0 + 192 ]
61 # qhasm: t1 = mem64[ input_0 + 200 ]
91 # qhasm: t0 = mem64[ input_0 + 176 ]
96 # qhasm: t1 = mem64[ input_0 + 184 ]
126 # qhasm: t0 = mem64[ input_0 + 160 ]
131 # qhasm: t1 = mem64[ input_0 + 168 ]
161 # qhasm: t0 = mem64[ input_0 + 144 ]
166 # qhasm: t1 = mem64[ input_0 + 152 ]
266 # qhasm: t0 = mem64[ input_0 + 96 ]
476 # qhasm: t0 = mem64[ input_0 + 0 ]
[all …]
/dports/security/liboqs/liboqs-0.7.0/src/kem/classic_mceliece/pqclean_mceliece460896_avx/
H A Dupdate_asm.S54 # qhasm: s0 = mem64[ input_0 + 0 ]
59 # qhasm: s1 = mem64[ input_0 + 8 ]
79 # qhasm: mem64[ input_0 + 0 ] = s0
84 # qhasm: mem64[ input_0 + 8 ] = s1
94 # qhasm: s0 = mem64[ input_0 + 0 ]
99 # qhasm: s1 = mem64[ input_0 + 8 ]
119 # qhasm: mem64[ input_0 + 0 ] = s0
124 # qhasm: mem64[ input_0 + 8 ] = s1
134 # qhasm: s0 = mem64[ input_0 + 0 ]
139 # qhasm: s1 = mem64[ input_0 + 8 ]
[all …]
H A Dvec_reduce_asm.S56 # qhasm: t0 = mem64[ input_0 + 192 ]
61 # qhasm: t1 = mem64[ input_0 + 200 ]
91 # qhasm: t0 = mem64[ input_0 + 176 ]
96 # qhasm: t1 = mem64[ input_0 + 184 ]
126 # qhasm: t0 = mem64[ input_0 + 160 ]
131 # qhasm: t1 = mem64[ input_0 + 168 ]
161 # qhasm: t0 = mem64[ input_0 + 144 ]
166 # qhasm: t1 = mem64[ input_0 + 152 ]
266 # qhasm: t0 = mem64[ input_0 + 96 ]
476 # qhasm: t0 = mem64[ input_0 + 0 ]
[all …]
/dports/security/liboqs/liboqs-0.7.0/src/kem/classic_mceliece/pqclean_mceliece6960119_avx/
H A Dupdate_asm.S54 # qhasm: s0 = mem64[ input_0 + 0 ]
59 # qhasm: s1 = mem64[ input_0 + 8 ]
79 # qhasm: mem64[ input_0 + 0 ] = s0
84 # qhasm: mem64[ input_0 + 8 ] = s1
94 # qhasm: s0 = mem64[ input_0 + 0 ]
99 # qhasm: s1 = mem64[ input_0 + 8 ]
119 # qhasm: mem64[ input_0 + 0 ] = s0
124 # qhasm: mem64[ input_0 + 8 ] = s1
134 # qhasm: s0 = mem64[ input_0 + 0 ]
139 # qhasm: s1 = mem64[ input_0 + 8 ]
[all …]
H A Dvec_reduce_asm.S56 # qhasm: t0 = mem64[ input_0 + 192 ]
61 # qhasm: t1 = mem64[ input_0 + 200 ]
91 # qhasm: t0 = mem64[ input_0 + 176 ]
96 # qhasm: t1 = mem64[ input_0 + 184 ]
126 # qhasm: t0 = mem64[ input_0 + 160 ]
131 # qhasm: t1 = mem64[ input_0 + 168 ]
161 # qhasm: t0 = mem64[ input_0 + 144 ]
166 # qhasm: t1 = mem64[ input_0 + 152 ]
266 # qhasm: t0 = mem64[ input_0 + 96 ]
476 # qhasm: t0 = mem64[ input_0 + 0 ]
[all …]
/dports/security/liboqs/liboqs-0.7.0/src/kem/classic_mceliece/pqclean_mceliece348864f_avx/
H A Dupdate_asm.S52 # qhasm: s0 = mem64[ input_0 + 0 ]
67 # qhasm: mem64[ input_0 + 0 ] = s0
77 # qhasm: s0 = mem64[ input_0 + 0 ]
92 # qhasm: mem64[ input_0 + 0 ] = s0
102 # qhasm: s0 = mem64[ input_0 + 0 ]
117 # qhasm: mem64[ input_0 + 0 ] = s0
127 # qhasm: s0 = mem64[ input_0 + 0 ]
142 # qhasm: mem64[ input_0 + 0 ] = s0
152 # qhasm: s0 = mem64[ input_0 + 0 ]
167 # qhasm: mem64[ input_0 + 0 ] = s0
[all …]
/dports/security/liboqs/liboqs-0.7.0/src/kem/classic_mceliece/pqclean_mceliece348864_avx/
H A Dupdate_asm.S52 # qhasm: s0 = mem64[ input_0 + 0 ]
67 # qhasm: mem64[ input_0 + 0 ] = s0
77 # qhasm: s0 = mem64[ input_0 + 0 ]
92 # qhasm: mem64[ input_0 + 0 ] = s0
102 # qhasm: s0 = mem64[ input_0 + 0 ]
117 # qhasm: mem64[ input_0 + 0 ] = s0
127 # qhasm: s0 = mem64[ input_0 + 0 ]
142 # qhasm: mem64[ input_0 + 0 ] = s0
152 # qhasm: s0 = mem64[ input_0 + 0 ]
167 # qhasm: mem64[ input_0 + 0 ] = s0
[all …]
/dports/net/cjdns/cjdns-cjdns-v21.1/node_build/dependencies/cnacl/crypto_scalarmult/curve25519/neon2/
H A Dscalarmult.pq292 mem64[posx] aligned= f8[0] ;\
1470 h0 = mem64[p] h0[1]
1471 h1 = mem64[p] h1[1]
1473 h2 = mem64[p] h2[1]
1474 h3 = mem64[p] h3[1]
1476 h4 = mem64[p] h4[1]
1478 h5 = mem64[p] h5[1]
1479 h6 = mem64[p] h6[1]
1481 h7 = mem64[p] h7[1]
1483 h8 = mem64[p] h8[1]
[all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/clang/test/CodeGen/
H A Dbuiltins-systemz.c12 void test_htm1(struct __htm_tdb *tdb, int reg, int *mem, uint64_t *mem64) { in test_htm1() argument
75 __builtin_non_tx_store (mem64, 0); in test_htm1()
78 __builtin_non_tx_store (mem64, val_var); in test_htm1()
80 __builtin_non_tx_store (mem64, (uint64_t)reg); in test_htm1()
82 __builtin_non_tx_store (mem64, g); in test_htm1()
/dports/devel/llvm11/llvm-11.0.1.src/tools/clang/test/CodeGen/
H A Dbuiltins-systemz.c12 void test_htm1(struct __htm_tdb *tdb, int reg, int *mem, uint64_t *mem64) { in test_htm1() argument
75 __builtin_non_tx_store (mem64, 0); in test_htm1()
78 __builtin_non_tx_store (mem64, val_var); in test_htm1()
80 __builtin_non_tx_store (mem64, (uint64_t)reg); in test_htm1()
82 __builtin_non_tx_store (mem64, g); in test_htm1()

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