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Searched refs:mfdcr (Results 1 – 25 of 450) sorted by relevance

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/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/powerpc/platforms/44x/
H A Dfsp2.c152 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_MCSTAT)); in mcue_handler()
160 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR0)); in mcue_handler()
162 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR1)); in mcue_handler()
164 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR2)); in mcue_handler()
166 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR3)); in mcue_handler()
178 mfdcr(DCRN_CW_BASE + DCRN_CW_MCER0)); in mcue_handler()
180 mfdcr(DCRN_CW_BASE + DCRN_CW_MCER1)); in mcue_handler()
182 mfdcr(DCRN_PLB6MCIF_BESR0)); in mcue_handler()
184 mfdcr(DCRN_PLB6MCIF_BEARL)); in mcue_handler()
186 mfdcr(DCRN_PLB6MCIF_BEARH)); in mcue_handler()
[all …]
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/powerpc/platforms/44x/
H A Dfsp2.c152 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_MCSTAT)); in mcue_handler()
160 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR0)); in mcue_handler()
162 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR1)); in mcue_handler()
164 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR2)); in mcue_handler()
166 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR3)); in mcue_handler()
178 mfdcr(DCRN_CW_BASE + DCRN_CW_MCER0)); in mcue_handler()
180 mfdcr(DCRN_CW_BASE + DCRN_CW_MCER1)); in mcue_handler()
182 mfdcr(DCRN_PLB6MCIF_BESR0)); in mcue_handler()
184 mfdcr(DCRN_PLB6MCIF_BEARL)); in mcue_handler()
186 mfdcr(DCRN_PLB6MCIF_BEARH)); in mcue_handler()
[all …]
/dports/multimedia/libv4l/linux-5.13-rc2/arch/powerpc/platforms/44x/
H A Dfsp2.c152 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_MCSTAT)); in mcue_handler()
160 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR0)); in mcue_handler()
162 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR1)); in mcue_handler()
164 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR2)); in mcue_handler()
166 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR3)); in mcue_handler()
178 mfdcr(DCRN_CW_BASE + DCRN_CW_MCER0)); in mcue_handler()
180 mfdcr(DCRN_CW_BASE + DCRN_CW_MCER1)); in mcue_handler()
182 mfdcr(DCRN_PLB6MCIF_BESR0)); in mcue_handler()
184 mfdcr(DCRN_PLB6MCIF_BEARL)); in mcue_handler()
186 mfdcr(DCRN_PLB6MCIF_BEARH)); in mcue_handler()
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/
H A Ddenali_data_eye.c84 val = mfdcr(ddrcfgd); in wait_for_dram_init_complete()
139 val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | in denali_core_search_data_eye()
147 val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) | in denali_core_search_data_eye()
156 val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) | in denali_core_search_data_eye()
193 mfdcr(ddrcfgd) | DDR0_00_INT_ACK_ENCODE(0x3C)); in denali_core_search_data_eye()
202 val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | in denali_core_search_data_eye()
258 || (DDR0_00_INT_STATUS_DECODE(mfdcr(ddrcfgd)) & in denali_core_search_data_eye()
284 val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | in denali_core_search_data_eye()
317 val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) in denali_core_search_data_eye()
327 val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) in denali_core_search_data_eye()
[all …]
H A Duic.c112 uic_msr = mfdcr(UIC0MSR); in external_interrupt()
159 mtdcr(UIC0ER, mfdcr(UIC0ER) | UIC_MASK(vec)); in pic_irq_enable()
161 mtdcr(UIC1ER, mfdcr(UIC1ER) | UIC_MASK(vec)); in pic_irq_enable()
163 mtdcr(UIC2ER, mfdcr(UIC2ER) | UIC_MASK(vec)); in pic_irq_enable()
165 mtdcr(UIC3ER, mfdcr(UIC3ER) | UIC_MASK(vec)); in pic_irq_enable()
173 mtdcr(UIC0ER, mfdcr(UIC0ER) & ~UIC_MASK(vec)); in pic_irq_disable()
175 mtdcr(UIC1ER, mfdcr(UIC1ER) & ~UIC_MASK(vec)); in pic_irq_disable()
177 mtdcr(UIC2ER, mfdcr(UIC2ER) & ~UIC_MASK(vec)); in pic_irq_disable()
179 mtdcr(UIC3ER, mfdcr(UIC3ER) & ~UIC_MASK(vec)); in pic_irq_disable()
H A Dcpu.c68 return (mfdcr(CPC0_PSR) & PSR_PCI_ASYNC_EN); in pci_async_enabled()
88 return (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN); in pci_arbiter_enabled()
92 return (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN); in pci_arbiter_enabled()
96 return (mfdcr(CPC0_STRP1) & CPC0_STRP1_PAE_MASK); in pci_arbiter_enabled()
122 return (mfdcr(CPC0_BOOT) & CPC0_BOOT_SEP); in i2c_bootrom_enabled()
272 mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) | 0x80000000); /* Set SWE */ in do_chip_reset()
275 mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) & ~0x80000000); /* Clr SWE */ in do_chip_reset()
424 if ((mfdcr(CPC0_SYS0) != mfdcr(CPC0_STRP0)) || in checkcpu()
425 (mfdcr(CPC0_SYS1) != mfdcr(CPC0_STRP1)) ){ in checkcpu()
429 do_chip_reset ( mfdcr(CPC0_STRP0), in checkcpu()
[all …]
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/
H A Ddenali_data_eye.c84 val = mfdcr(ddrcfgd); in wait_for_dram_init_complete()
139 val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | in denali_core_search_data_eye()
147 val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) | in denali_core_search_data_eye()
156 val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) | in denali_core_search_data_eye()
193 mfdcr(ddrcfgd) | DDR0_00_INT_ACK_ENCODE(0x3C)); in denali_core_search_data_eye()
202 val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | in denali_core_search_data_eye()
258 || (DDR0_00_INT_STATUS_DECODE(mfdcr(ddrcfgd)) & in denali_core_search_data_eye()
284 val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | in denali_core_search_data_eye()
317 val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) in denali_core_search_data_eye()
327 val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) in denali_core_search_data_eye()
[all …]
H A Duic.c112 uic_msr = mfdcr(UIC0MSR); in external_interrupt()
159 mtdcr(UIC0ER, mfdcr(UIC0ER) | UIC_MASK(vec)); in pic_irq_enable()
161 mtdcr(UIC1ER, mfdcr(UIC1ER) | UIC_MASK(vec)); in pic_irq_enable()
163 mtdcr(UIC2ER, mfdcr(UIC2ER) | UIC_MASK(vec)); in pic_irq_enable()
165 mtdcr(UIC3ER, mfdcr(UIC3ER) | UIC_MASK(vec)); in pic_irq_enable()
173 mtdcr(UIC0ER, mfdcr(UIC0ER) & ~UIC_MASK(vec)); in pic_irq_disable()
175 mtdcr(UIC1ER, mfdcr(UIC1ER) & ~UIC_MASK(vec)); in pic_irq_disable()
177 mtdcr(UIC2ER, mfdcr(UIC2ER) & ~UIC_MASK(vec)); in pic_irq_disable()
179 mtdcr(UIC3ER, mfdcr(UIC3ER) & ~UIC_MASK(vec)); in pic_irq_disable()
H A Dcpu.c68 return (mfdcr(CPC0_PSR) & PSR_PCI_ASYNC_EN); in pci_async_enabled()
88 return (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN); in pci_arbiter_enabled()
92 return (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN); in pci_arbiter_enabled()
96 return (mfdcr(CPC0_STRP1) & CPC0_STRP1_PAE_MASK); in pci_arbiter_enabled()
122 return (mfdcr(CPC0_BOOT) & CPC0_BOOT_SEP); in i2c_bootrom_enabled()
272 mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) | 0x80000000); /* Set SWE */ in do_chip_reset()
275 mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) & ~0x80000000); /* Clr SWE */ in do_chip_reset()
424 if ((mfdcr(CPC0_SYS0) != mfdcr(CPC0_STRP0)) || in checkcpu()
425 (mfdcr(CPC0_SYS1) != mfdcr(CPC0_STRP1)) ){ in checkcpu()
429 do_chip_reset ( mfdcr(CPC0_STRP0), in checkcpu()
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/
H A Ddenali_data_eye.c84 val = mfdcr(ddrcfgd); in wait_for_dram_init_complete()
139 val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | in denali_core_search_data_eye()
147 val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) | in denali_core_search_data_eye()
156 val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) | in denali_core_search_data_eye()
193 mfdcr(ddrcfgd) | DDR0_00_INT_ACK_ENCODE(0x3C)); in denali_core_search_data_eye()
202 val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | in denali_core_search_data_eye()
258 || (DDR0_00_INT_STATUS_DECODE(mfdcr(ddrcfgd)) & in denali_core_search_data_eye()
284 val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | in denali_core_search_data_eye()
317 val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) in denali_core_search_data_eye()
327 val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) in denali_core_search_data_eye()
[all …]
H A Duic.c112 uic_msr = mfdcr(UIC0MSR); in external_interrupt()
159 mtdcr(UIC0ER, mfdcr(UIC0ER) | UIC_MASK(vec)); in pic_irq_enable()
161 mtdcr(UIC1ER, mfdcr(UIC1ER) | UIC_MASK(vec)); in pic_irq_enable()
163 mtdcr(UIC2ER, mfdcr(UIC2ER) | UIC_MASK(vec)); in pic_irq_enable()
165 mtdcr(UIC3ER, mfdcr(UIC3ER) | UIC_MASK(vec)); in pic_irq_enable()
173 mtdcr(UIC0ER, mfdcr(UIC0ER) & ~UIC_MASK(vec)); in pic_irq_disable()
175 mtdcr(UIC1ER, mfdcr(UIC1ER) & ~UIC_MASK(vec)); in pic_irq_disable()
177 mtdcr(UIC2ER, mfdcr(UIC2ER) & ~UIC_MASK(vec)); in pic_irq_disable()
179 mtdcr(UIC3ER, mfdcr(UIC3ER) & ~UIC_MASK(vec)); in pic_irq_disable()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/
H A Ddenali_data_eye.c84 val = mfdcr(ddrcfgd); in wait_for_dram_init_complete()
139 val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | in denali_core_search_data_eye()
147 val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) | in denali_core_search_data_eye()
156 val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) | in denali_core_search_data_eye()
193 mfdcr(ddrcfgd) | DDR0_00_INT_ACK_ENCODE(0x3C)); in denali_core_search_data_eye()
202 val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | in denali_core_search_data_eye()
258 || (DDR0_00_INT_STATUS_DECODE(mfdcr(ddrcfgd)) & in denali_core_search_data_eye()
284 val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | in denali_core_search_data_eye()
317 val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) in denali_core_search_data_eye()
327 val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) in denali_core_search_data_eye()
[all …]
H A Duic.c112 uic_msr = mfdcr(UIC0MSR); in external_interrupt()
159 mtdcr(UIC0ER, mfdcr(UIC0ER) | UIC_MASK(vec)); in pic_irq_enable()
161 mtdcr(UIC1ER, mfdcr(UIC1ER) | UIC_MASK(vec)); in pic_irq_enable()
163 mtdcr(UIC2ER, mfdcr(UIC2ER) | UIC_MASK(vec)); in pic_irq_enable()
165 mtdcr(UIC3ER, mfdcr(UIC3ER) | UIC_MASK(vec)); in pic_irq_enable()
173 mtdcr(UIC0ER, mfdcr(UIC0ER) & ~UIC_MASK(vec)); in pic_irq_disable()
175 mtdcr(UIC1ER, mfdcr(UIC1ER) & ~UIC_MASK(vec)); in pic_irq_disable()
177 mtdcr(UIC2ER, mfdcr(UIC2ER) & ~UIC_MASK(vec)); in pic_irq_disable()
179 mtdcr(UIC3ER, mfdcr(UIC3ER) & ~UIC_MASK(vec)); in pic_irq_disable()
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/
H A Ddenali_data_eye.c84 val = mfdcr(ddrcfgd); in wait_for_dram_init_complete()
139 val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | in denali_core_search_data_eye()
147 val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) | in denali_core_search_data_eye()
156 val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) | in denali_core_search_data_eye()
193 mfdcr(ddrcfgd) | DDR0_00_INT_ACK_ENCODE(0x3C)); in denali_core_search_data_eye()
202 val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | in denali_core_search_data_eye()
258 || (DDR0_00_INT_STATUS_DECODE(mfdcr(ddrcfgd)) & in denali_core_search_data_eye()
284 val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | in denali_core_search_data_eye()
317 val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) in denali_core_search_data_eye()
327 val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) in denali_core_search_data_eye()
[all …]
H A Duic.c112 uic_msr = mfdcr(UIC0MSR); in external_interrupt()
159 mtdcr(UIC0ER, mfdcr(UIC0ER) | UIC_MASK(vec)); in pic_irq_enable()
161 mtdcr(UIC1ER, mfdcr(UIC1ER) | UIC_MASK(vec)); in pic_irq_enable()
163 mtdcr(UIC2ER, mfdcr(UIC2ER) | UIC_MASK(vec)); in pic_irq_enable()
165 mtdcr(UIC3ER, mfdcr(UIC3ER) | UIC_MASK(vec)); in pic_irq_enable()
173 mtdcr(UIC0ER, mfdcr(UIC0ER) & ~UIC_MASK(vec)); in pic_irq_disable()
175 mtdcr(UIC1ER, mfdcr(UIC1ER) & ~UIC_MASK(vec)); in pic_irq_disable()
177 mtdcr(UIC2ER, mfdcr(UIC2ER) & ~UIC_MASK(vec)); in pic_irq_disable()
179 mtdcr(UIC3ER, mfdcr(UIC3ER) & ~UIC_MASK(vec)); in pic_irq_disable()
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/
H A Ddenali_data_eye.c84 val = mfdcr(ddrcfgd); in wait_for_dram_init_complete()
139 val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | in denali_core_search_data_eye()
147 val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) | in denali_core_search_data_eye()
156 val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) | in denali_core_search_data_eye()
193 mfdcr(ddrcfgd) | DDR0_00_INT_ACK_ENCODE(0x3C)); in denali_core_search_data_eye()
202 val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | in denali_core_search_data_eye()
258 || (DDR0_00_INT_STATUS_DECODE(mfdcr(ddrcfgd)) & in denali_core_search_data_eye()
284 val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | in denali_core_search_data_eye()
317 val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) in denali_core_search_data_eye()
327 val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) in denali_core_search_data_eye()
[all …]
H A Duic.c112 uic_msr = mfdcr(UIC0MSR); in external_interrupt()
159 mtdcr(UIC0ER, mfdcr(UIC0ER) | UIC_MASK(vec)); in pic_irq_enable()
161 mtdcr(UIC1ER, mfdcr(UIC1ER) | UIC_MASK(vec)); in pic_irq_enable()
163 mtdcr(UIC2ER, mfdcr(UIC2ER) | UIC_MASK(vec)); in pic_irq_enable()
165 mtdcr(UIC3ER, mfdcr(UIC3ER) | UIC_MASK(vec)); in pic_irq_enable()
173 mtdcr(UIC0ER, mfdcr(UIC0ER) & ~UIC_MASK(vec)); in pic_irq_disable()
175 mtdcr(UIC1ER, mfdcr(UIC1ER) & ~UIC_MASK(vec)); in pic_irq_disable()
177 mtdcr(UIC2ER, mfdcr(UIC2ER) & ~UIC_MASK(vec)); in pic_irq_disable()
179 mtdcr(UIC3ER, mfdcr(UIC3ER) & ~UIC_MASK(vec)); in pic_irq_disable()
/dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/powerpc/cpu/ppc4xx/
H A Ddenali_data_eye.c71 val = mfdcr(ddrcfgd); in wait_for_dram_init_complete()
126 val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | in denali_core_search_data_eye()
134 val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) | in denali_core_search_data_eye()
143 val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) | in denali_core_search_data_eye()
180 mfdcr(ddrcfgd) | DDR0_00_INT_ACK_ENCODE(0x3C)); in denali_core_search_data_eye()
189 val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | in denali_core_search_data_eye()
245 || (DDR0_00_INT_STATUS_DECODE(mfdcr(ddrcfgd)) & in denali_core_search_data_eye()
271 val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | in denali_core_search_data_eye()
304 val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) in denali_core_search_data_eye()
314 val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) in denali_core_search_data_eye()
[all …]
H A Duic.c96 uic_msr = mfdcr(UIC0MSR); in external_interrupt()
143 mtdcr(UIC0ER, mfdcr(UIC0ER) | UIC_MASK(vec)); in pic_irq_enable()
145 mtdcr(UIC1ER, mfdcr(UIC1ER) | UIC_MASK(vec)); in pic_irq_enable()
147 mtdcr(UIC2ER, mfdcr(UIC2ER) | UIC_MASK(vec)); in pic_irq_enable()
149 mtdcr(UIC3ER, mfdcr(UIC3ER) | UIC_MASK(vec)); in pic_irq_enable()
157 mtdcr(UIC0ER, mfdcr(UIC0ER) & ~UIC_MASK(vec)); in pic_irq_disable()
159 mtdcr(UIC1ER, mfdcr(UIC1ER) & ~UIC_MASK(vec)); in pic_irq_disable()
161 mtdcr(UIC2ER, mfdcr(UIC2ER) & ~UIC_MASK(vec)); in pic_irq_disable()
163 mtdcr(UIC3ER, mfdcr(UIC3ER) & ~UIC_MASK(vec)); in pic_irq_disable()
H A Dcpu.c51 return (mfdcr(CPC0_PSR) & PSR_PCI_ASYNC_EN); in pci_async_enabled()
71 return (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN); in pci_arbiter_enabled()
75 return (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN); in pci_arbiter_enabled()
79 return (mfdcr(CPC0_STRP1) & CPC0_STRP1_PAE_MASK); in pci_arbiter_enabled()
105 return (mfdcr(CPC0_BOOT) & CPC0_BOOT_SEP); in i2c_bootrom_enabled()
255 mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) | 0x80000000); /* Set SWE */ in do_chip_reset()
258 mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) & ~0x80000000); /* Clr SWE */ in do_chip_reset()
381 if ((mfdcr(CPC0_SYS0) != mfdcr(CPC0_STRP0)) || in checkcpu()
382 (mfdcr(CPC0_SYS1) != mfdcr(CPC0_STRP1)) ){ in checkcpu()
386 do_chip_reset ( mfdcr(CPC0_STRP0), in checkcpu()
[all …]
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/
H A Ddenali_data_eye.c84 val = mfdcr(ddrcfgd); in wait_for_dram_init_complete()
139 val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | in denali_core_search_data_eye()
147 val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) | in denali_core_search_data_eye()
156 val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) | in denali_core_search_data_eye()
193 mfdcr(ddrcfgd) | DDR0_00_INT_ACK_ENCODE(0x3C)); in denali_core_search_data_eye()
202 val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | in denali_core_search_data_eye()
258 || (DDR0_00_INT_STATUS_DECODE(mfdcr(ddrcfgd)) & in denali_core_search_data_eye()
284 val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | in denali_core_search_data_eye()
317 val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) in denali_core_search_data_eye()
327 val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) in denali_core_search_data_eye()
[all …]
H A Duic.c112 uic_msr = mfdcr(UIC0MSR); in external_interrupt()
159 mtdcr(UIC0ER, mfdcr(UIC0ER) | UIC_MASK(vec)); in pic_irq_enable()
161 mtdcr(UIC1ER, mfdcr(UIC1ER) | UIC_MASK(vec)); in pic_irq_enable()
163 mtdcr(UIC2ER, mfdcr(UIC2ER) | UIC_MASK(vec)); in pic_irq_enable()
165 mtdcr(UIC3ER, mfdcr(UIC3ER) | UIC_MASK(vec)); in pic_irq_enable()
173 mtdcr(UIC0ER, mfdcr(UIC0ER) & ~UIC_MASK(vec)); in pic_irq_disable()
175 mtdcr(UIC1ER, mfdcr(UIC1ER) & ~UIC_MASK(vec)); in pic_irq_disable()
177 mtdcr(UIC2ER, mfdcr(UIC2ER) & ~UIC_MASK(vec)); in pic_irq_disable()
179 mtdcr(UIC3ER, mfdcr(UIC3ER) & ~UIC_MASK(vec)); in pic_irq_disable()
/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/powerpc/platforms/4xx/
H A Dsoc.c36 while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC)) in l2c_diag()
39 return mfdcr(dcrbase_l2c + DCRN_L2C0_DATA); in l2c_diag()
44 u32 sr = mfdcr(dcrbase_l2c + DCRN_L2C0_SR); in l2c_error_handler()
126 mfdcr(dcrbase_isram + DCRN_SRAM0_DPC) & ~SRAM_DPC_ENABLE); in ppc4xx_l2c_probe()
128 mfdcr(dcrbase_isram + DCRN_SRAM0_SB0CR) & ~SRAM_SBCR_BU_MASK); in ppc4xx_l2c_probe()
130 mfdcr(dcrbase_isram + DCRN_SRAM0_SB1CR) & ~SRAM_SBCR_BU_MASK); in ppc4xx_l2c_probe()
137 r = mfdcr(dcrbase_l2c + DCRN_L2C0_CFG) & in ppc4xx_l2c_probe()
146 while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC)) in ppc4xx_l2c_probe()
153 r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP0) & in ppc4xx_l2c_probe()
158 r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP1) & in ppc4xx_l2c_probe()
[all …]
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/powerpc/platforms/4xx/
H A Dsoc.c36 while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC)) in l2c_diag()
39 return mfdcr(dcrbase_l2c + DCRN_L2C0_DATA); in l2c_diag()
44 u32 sr = mfdcr(dcrbase_l2c + DCRN_L2C0_SR); in l2c_error_handler()
126 mfdcr(dcrbase_isram + DCRN_SRAM0_DPC) & ~SRAM_DPC_ENABLE); in ppc4xx_l2c_probe()
128 mfdcr(dcrbase_isram + DCRN_SRAM0_SB0CR) & ~SRAM_SBCR_BU_MASK); in ppc4xx_l2c_probe()
130 mfdcr(dcrbase_isram + DCRN_SRAM0_SB1CR) & ~SRAM_SBCR_BU_MASK); in ppc4xx_l2c_probe()
137 r = mfdcr(dcrbase_l2c + DCRN_L2C0_CFG) & in ppc4xx_l2c_probe()
146 while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC)) in ppc4xx_l2c_probe()
153 r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP0) & in ppc4xx_l2c_probe()
158 r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP1) & in ppc4xx_l2c_probe()
[all …]
/dports/multimedia/libv4l/linux-5.13-rc2/arch/powerpc/platforms/4xx/
H A Dsoc.c36 while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC)) in l2c_diag()
39 return mfdcr(dcrbase_l2c + DCRN_L2C0_DATA); in l2c_diag()
44 u32 sr = mfdcr(dcrbase_l2c + DCRN_L2C0_SR); in l2c_error_handler()
126 mfdcr(dcrbase_isram + DCRN_SRAM0_DPC) & ~SRAM_DPC_ENABLE); in ppc4xx_l2c_probe()
128 mfdcr(dcrbase_isram + DCRN_SRAM0_SB0CR) & ~SRAM_SBCR_BU_MASK); in ppc4xx_l2c_probe()
130 mfdcr(dcrbase_isram + DCRN_SRAM0_SB1CR) & ~SRAM_SBCR_BU_MASK); in ppc4xx_l2c_probe()
137 r = mfdcr(dcrbase_l2c + DCRN_L2C0_CFG) & in ppc4xx_l2c_probe()
146 while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC)) in ppc4xx_l2c_probe()
153 r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP0) & in ppc4xx_l2c_probe()
158 r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP1) & in ppc4xx_l2c_probe()
[all …]

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