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Searched refs:mmSDMA0_UTCL1_CNTL (Results 1 – 24 of 24) sorted by relevance

/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h132 #define mmSDMA0_UTCL1_CNTL … macro
H A Dsdma0_4_0_offset.h134 #define mmSDMA0_UTCL1_CNTL 0x003c macro
H A Dsdma0_4_2_offset.h134 #define mmSDMA0_UTCL1_CNTL … macro
H A Dsdma0_4_2_2_offset.h134 #define mmSDMA0_UTCL1_CNTL … macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h132 #define mmSDMA0_UTCL1_CNTL … macro
H A Dsdma0_4_0_offset.h134 #define mmSDMA0_UTCL1_CNTL 0x003c macro
H A Dsdma0_4_2_offset.h134 #define mmSDMA0_UTCL1_CNTL … macro
H A Dsdma0_4_2_2_offset.h134 #define mmSDMA0_UTCL1_CNTL … macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h132 #define mmSDMA0_UTCL1_CNTL … macro
H A Dsdma0_4_0_offset.h134 #define mmSDMA0_UTCL1_CNTL 0x003c macro
H A Dsdma0_4_2_2_offset.h134 #define mmSDMA0_UTCL1_CNTL … macro
H A Dsdma0_4_2_offset.h134 #define mmSDMA0_UTCL1_CNTL … macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v5_0.c752 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); in sdma_v5_0_gfx_resume()
755 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); in sdma_v5_0_gfx_resume()
H A Dsdma_v5_2.c709 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); in sdma_v5_2_gfx_resume()
712 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); in sdma_v5_2_gfx_resume()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v5_0.c752 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); in sdma_v5_0_gfx_resume()
755 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); in sdma_v5_0_gfx_resume()
H A Dsdma_v5_2.c709 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); in sdma_v5_2_gfx_resume()
712 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); in sdma_v5_2_gfx_resume()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v5_0.c752 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); in sdma_v5_0_gfx_resume()
755 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); in sdma_v5_0_gfx_resume()
H A Dsdma_v5_2.c709 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); in sdma_v5_2_gfx_resume()
712 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); in sdma_v5_2_gfx_resume()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h109 #define mmSDMA0_UTCL1_CNTL … macro
H A Dgc_10_3_0_offset.h106 #define mmSDMA0_UTCL1_CNTL … macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h109 #define mmSDMA0_UTCL1_CNTL … macro
H A Dgc_10_3_0_offset.h106 #define mmSDMA0_UTCL1_CNTL … macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h109 #define mmSDMA0_UTCL1_CNTL … macro
H A Dgc_10_3_0_offset.h106 #define mmSDMA0_UTCL1_CNTL … macro