/dports/graphics/svgalib/svgalib-1.4.3/src/ |
H A D | vgaregs.c | 47 moderegs[VGA_SR0] = 0x00; in __svgalib_setup_VGA_registers() 49 moderegs[VGA_SR0] = 0x02; in __svgalib_setup_VGA_registers() 50 moderegs[VGA_SR1] = 0x01; in __svgalib_setup_VGA_registers() 52 moderegs[VGA_SR3] = 0x00; in __svgalib_setup_VGA_registers() 53 moderegs[VGA_SR4] = 0x0E; in __svgalib_setup_VGA_registers() 55 moderegs[VGA_SR4] = 0x06; in __svgalib_setup_VGA_registers() 74 moderegs[VGA_CR8] = 0x00; in __svgalib_setup_VGA_registers() 77 moderegs[VGA_CR9] |= 0x80; in __svgalib_setup_VGA_registers() 93 moderegs[VGA_CR17] = 0xE3; in __svgalib_setup_VGA_registers() 104 moderegs[VGA_GR5] = 0x02; in __svgalib_setup_VGA_registers() [all …]
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H A D | mx.c | 294 p=moderegs[1]+((moderegs[MXREG_SAVE(1)]&2)<<7); in mx_initializemode() 295 moderegs[2]=p&0xff; in mx_initializemode() 300 q=moderegs[4]+((moderegs[MXREG_SAVE(1)]&8)<<5); in mx_initializemode() 301 r=moderegs[0]+4; in mx_initializemode() 302 moderegs[3]&=0xe0; in mx_initializemode() 304 moderegs[5]&=0x7f; in mx_initializemode() 307 p=moderegs[0x12]+((moderegs[0x7]&2)<<7)+((moderegs[7]&0x40)<<3)+((moderegs[MXREG_SAVE(2)]&2)<<9); in mx_initializemode() 309 moderegs[0x7]&=0xf7; in mx_initializemode() 311 moderegs[0x9]&=0xdf; in mx_initializemode() 317 moderegs[0x16]=moderegs[6]+1; in mx_initializemode() [all …]
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H A D | apm.c | 322 moderegs[MIS]=0xef; in apm_initializemode() 331 p=moderegs[1]+((moderegs[APMREG_SAVE(4)]&2)<<7); in apm_initializemode() 332 moderegs[2]=p&0xff; in apm_initializemode() 335 q=moderegs[4]+((moderegs[APMREG_SAVE(4)]&8)<<5); in apm_initializemode() 336 r=moderegs[0]+4; in apm_initializemode() 337 moderegs[3]&=0xe0; in apm_initializemode() 339 moderegs[5]&=0x7f; in apm_initializemode() 342 p=moderegs[0x12]+((moderegs[0x7]&2)<<7)+((moderegs[7]&0x40)<<3)+((moderegs[APMREG_SAVE(3)]&2)<<9); in apm_initializemode() 344 moderegs[0x7]&=0xf7; in apm_initializemode() 350 moderegs[0x16]=moderegs[6]+1; in apm_initializemode() [all …]
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H A D | s3.c | 677 s3_saveregs(moderegs); in s3_initializemode() 690 moderegs[S3_CR31] = 0x8F; in s3_initializemode() 692 moderegs[S3_CR31] = 0x8D; in s3_initializemode() 702 moderegs[S3_CR32] = 0; in s3_initializemode() 723 moderegs[S3_CR3B] = (moderegs[VGA_CR0] + moderegs[VGA_CR4] + 1) / 2; in s3_initializemode() 724 moderegs[S3_CR3C] = moderegs[VGA_CR0] / 2; in s3_initializemode() 877 moderegs[S3_CR60] = n; in s3_initializemode() 906 moderegs[S3_CR5E] = in s3_initializemode() 934 moderegs[S3_CR3C] = (moderegs[VGA_CR0] + ((i & 0x01) << 8)) / 2; in s3_initializemode() 935 moderegs[S3_CR5D] = (moderegs[S3_CR5D] & 0x80) | i; in s3_initializemode() [all …]
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H A D | neo.c | 486 neo_saveregs(moderegs); in neo_initializemode() 489 moderegs[EXT_SAVED] = FALSE; in neo_initializemode() 509 moderegs[DAC + i*3+0] = i << 1; in neo_initializemode() 510 moderegs[DAC + i*3+1] = i; in neo_initializemode() 511 moderegs[DAC + i*3+2] = i << 1; in neo_initializemode() 518 moderegs[DAC + i*3+0] = i; in neo_initializemode() 519 moderegs[DAC + i*3+1] = i; in neo_initializemode() 520 moderegs[DAC + i*3+2] = i; in neo_initializemode() 652 moderegs[MIS] |= 0x0C; in neo_initializemode() 660 unsigned char *moderegs; in neo_setmode() local [all …]
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H A D | chips.c | 1242 moderegs[XR2F] = (moderegs[XR2F] & 0xDF) in CHIPS_initializemode() 1437 moderegs[HiQVFR20],moderegs[HiQVFR21],moderegs[HiQVFR22],moderegs[HiQVFR23], in CHIPS_HiQV_initializemode() 1438 moderegs[HiQVFR24],moderegs[HiQVFR25]); in CHIPS_HiQV_initializemode() 1440 moderegs[HiQVFR26],moderegs[HiQVFR27]); in CHIPS_HiQV_initializemode() 1442 moderegs[HiQVFR30],moderegs[HiQVFR31],moderegs[HiQVFR32],moderegs[HiQVFR33], in CHIPS_HiQV_initializemode() 1443 moderegs[HiQVFR34],moderegs[HiQVFR35]); in CHIPS_HiQV_initializemode() 1445 moderegs[HiQVFR36],moderegs[HiQVFR37]); in CHIPS_HiQV_initializemode() 1455 moderegs[HiQVFR26] = (moderegs[HiQVFR26] & ~0x1F) in CHIPS_HiQV_initializemode() 1474 moderegs[HiQVFR20],moderegs[HiQVFR21],moderegs[HiQVFR22],moderegs[HiQVFR23], in CHIPS_HiQV_initializemode() 1475 moderegs[HiQVFR24],moderegs[HiQVFR25]); in CHIPS_HiQV_initializemode() [all …]
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H A D | g400.c | 459 moderegs[0] = ht - 4; in g400_initializemode() 460 moderegs[1] = hd; in g400_initializemode() 461 moderegs[2] = hd; in g400_initializemode() 463 moderegs[4] = hs; in g400_initializemode() 465 moderegs[6] = vt & 0xFF; in g400_initializemode() 475 moderegs[16] = vs & 0xFF; in g400_initializemode() 477 moderegs[18] = vd & 0xFF; in g400_initializemode() 478 moderegs[19] = wd & 0xFF; in g400_initializemode() 483 moderegs[9] |= 0x80; in g400_initializemode() 485 moderegs[59] |= 0x0C; in g400_initializemode() [all …]
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H A D | nv3.c | 229 moderegs[NV3REG_SAVE(0)]= in CalculateCRTC() 239 moderegs[0x4]=Set8Bits(horizStart); in CalculateCRTC() 254 moderegs[0x10]= Set8Bits(vertStart); in CalculateCRTC() 287 nv3_saveregs(moderegs); in nv3_initializemode() 291 moderegs[NV3REG_SAVE(12)] = k&0xff; in nv3_initializemode() 298 moderegs[NV3REG_SAVE(1)]= in nv3_initializemode() 304 moderegs[NV3REG_SAVE(5)]=0x83; in nv3_initializemode() 305 moderegs[NV3REG_SAVE(6)]=0x22; in nv3_initializemode() 360 moderegs[88]=28; in nv3_initializemode() 372 unsigned char *moderegs; in nv3_setmode() local [all …]
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H A D | et6000.c | 163 moderegs[VGA_CR17] = 0xa3; in et6000_initializemode() 165 moderegs[VGA_CR17] = 0xab; in et6000_initializemode() 167 moderegs[VGA_CR14] = 0x40; in et6000_initializemode() 169 moderegs[VGA_CR14] = 0x60; in et6000_initializemode() 172 moderegs[VGA_AR11] = 0x00; in et6000_initializemode() 235 moderegs[et6ksav] &= 0xfe; in et6000_initializemode() 242 moderegs[et6ksav + 4] |= 2; in et6000_initializemode() 243 moderegs[VGA_MISCOUTPUT] = (moderegs[VGA_MISCOUTPUT] & 0xf3) | in et6000_initializemode() 617 unsigned char i,*moderegs; in et6000_setmode() local 674 __svgalib_setregs(moderegs); in et6000_setmode() [all …]
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H A D | sis.c | 250 sis_saveregs(moderegs); in sis_initializemode() 256 moderegs[ATT+16] = 0x01; in sis_initializemode() 257 moderegs[20] = 0x40; in sis_initializemode() 258 moderegs[23] = 0xA3; in sis_initializemode() 274 moderegs[BankReg] = 0x02; in sis_initializemode() 292 moderegs[BankReg] |= 0x10; in sis_initializemode() 304 moderegs[BankReg] |= 0x20; in sis_initializemode() 320 moderegs[XR(0x27)]&=0xf0; in sis_initializemode() 342 moderegs[59]=0x6f; in sis_initializemode() 350 unsigned char *moderegs; in sis_setmode() local [all …]
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H A D | ark.c | 265 ark_saveregs(moderegs); 277 moderegs[VGA_AR11] = 0x00; 279 moderegs[ARK_PELMASK] = 0xFF; 369 moderegs[ARK_INTERLACE_RETRACE] = 404 moderegs[VGA_MISCOUTPUT] &= ~0x0C; 405 moderegs[VGA_MISCOUTPUT] |= 408 moderegs[ARK_VIDEO_CLOCK_SELECT] |= 413 moderegs[VGA_SR1] |= 0x08; 439 unsigned char *moderegs; local 460 moderegs = malloc(ARK_TOTAL_REGS); [all …]
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H A D | cirrus.c | 429 cirrus_saveregs(moderegs); in cirrus_initializemode() 443 moderegs[CIRRUS_GRB] |= 0x20; in cirrus_initializemode() 454 moderegs[VGA_CR17] |= 0x04; in cirrus_initializemode() 455 moderegs[CIRRUS_CR1B] = 0x22; in cirrus_initializemode() 460 moderegs[CIRRUS_CR1A] = 0; in cirrus_initializemode() 467 moderegs[CIRRUS_CR19] = in cirrus_initializemode() 469 moderegs[CIRRUS_CR1A] |= 0x01; in cirrus_initializemode() 537 moderegs[CIRRUS_HIDDENDAC] = DAC; in cirrus_initializemode() 538 moderegs[CIRRUS_SR7] = SR7; in cirrus_initializemode() 598 unsigned char *moderegs; in cirrus_setmode() local [all …]
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H A D | banshee.c | 174 banshee_regs=(HWRecPtr)(moderegs+62); in banshee_initializemode() 176 banshee_saveregs(moderegs); in banshee_initializemode() 184 moderegs[BANSHEEREG_SAVE(0)]=((ht&0x100)>>8) | in banshee_initializemode() 195 moderegs[BANSHEEREG_SAVE(1)]=((vt & 0x400)>>10) | in banshee_initializemode() 238 moderegs[VGA_MISCOUTPUT]|=0x0c; in banshee_initializemode() 246 moderegs[41]=0; in banshee_initializemode() 249 moderegs[79]=0; in banshee_initializemode() 260 unsigned char *moderegs; in banshee_setmode() local 279 moderegs = malloc(BANSHEE_TOTAL_REGS); in banshee_setmode() 283 __svgalib_setregs(moderegs); /* Set standard regs. */ in banshee_setmode() [all …]
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H A D | savage.c | 509 j = ( moderegs[0] + ((i&0x01)<<8) in savage_initializemode() 510 + moderegs[4] + ((i&0x10)<<4) + 1) / 2; in savage_initializemode() 512 if (j-(moderegs[4] + ((i&0x10)<<4)) < 4) { in savage_initializemode() 513 if (moderegs[4] + ((i&0x10)<<4) + 4 <= moderegs[0]+ ((i&0x01)<<8)) in savage_initializemode() 514 j = moderegs[4] + ((i&0x10)<<4) + 4; in savage_initializemode() 516 j = moderegs[0]+ ((i&0x01)<<8) + 1; in savage_initializemode() 531 moderegs[19] = 0xFF & width; in savage_initializemode() 535 moderegs[VGA_MISCOUTPUT] |= 0x0c; in savage_initializemode() 599 unsigned char *moderegs; in savage_setmode() local 619 moderegs = malloc(SAVAGE_TOTAL_REGS); in savage_setmode() [all …]
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H A D | skeleton.c | 115 static void sk_initializemode(unsigned char *moderegs, in sk_initializemode() argument 121 __svgalib_setup_VGA_registers(moderegs, modetiming, modeinfo); in sk_initializemode() 129 unsigned char *moderegs; in sk_setmode() local 149 moderegs = malloc(SK_TOTAL_REGS); in sk_setmode() 151 sk_initializemode(moderegs, modetiming, modeinfo, mode); in sk_setmode() 154 __svgalib_setregs(moderegs); /* Set standard regs. */ in sk_setmode() 155 sk_setregs(moderegs, mode); /* Set extended regs. */ in sk_setmode() 156 free(moderegs); in sk_setmode()
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H A D | rage.c | 938 moderegs[GRA+0]=0; in rage_initializemode() 939 moderegs[GRA+1]=0; in rage_initializemode() 940 moderegs[GRA+2]=0; in rage_initializemode() 941 moderegs[GRA+3]=0; in rage_initializemode() 942 moderegs[GRA+4]=0; in rage_initializemode() 944 moderegs[GRA+6]=1; in rage_initializemode() 945 moderegs[GRA+7]=0; in rage_initializemode() 947 moderegs[SEQ+0]=0x3; in rage_initializemode() 948 moderegs[SEQ+1]=0x0; in rage_initializemode() 950 moderegs[SEQ+3]=0x0; in rage_initializemode() [all …]
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H A D | laguna.c | 269 static void laguna_initializemode(unsigned char *moderegs, in laguna_initializemode() argument 272 struct lagunahw *l=(struct lagunahw *)(moderegs+VGA_TOTAL_REGS); in laguna_initializemode() 278 __svgalib_setup_VGA_registers(moderegs, modetiming, modeinfo); in laguna_initializemode() 316 moderegs[0x13]=offset&0xff; in laguna_initializemode() 384 moderegs[59] |= 0x0c; in laguna_initializemode() 392 unsigned char *moderegs; in laguna_setmode() local 413 moderegs = malloc(LAGUNA_TOTAL_REGS); in laguna_setmode() 415 laguna_initializemode(moderegs, modetiming, modeinfo, mode); in laguna_setmode() 418 __svgalib_setregs(moderegs); /* Set standard regs. */ in laguna_setmode() 419 laguna_setregs(moderegs, mode); /* Set extended regs. */ in laguna_setmode() [all …]
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H A D | i740.c | 423 static void i740_initializemode(unsigned char *moderegs, in i740_initializemode() argument 431 new = (vgaI740Ptr)(moderegs+VGA_TOTAL_REGS); in i740_initializemode() 433 moderegs[0x13] = modeinfo->lineWidth >> 3; in i740_initializemode() 494 moderegs[0x11] = 0; in i740_initializemode() 504 moderegs[59] |= 0x0C; in i740_initializemode() 518 unsigned char *moderegs; in i740_setmode() local 538 moderegs = malloc(I740_TOTAL_REGS); in i740_setmode() 540 i740_initializemode(moderegs, modetiming, modeinfo, mode); in i740_setmode() 543 __svgalib_setregs(moderegs); /* Set standard regs. */ in i740_setmode() 544 i740_setregs(moderegs, mode); /* Set extended regs. */ in i740_setmode() [all …]
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H A D | r128.c | 880 static void r128_initializemode(unsigned char *moderegs, in r128_initializemode() argument 883 __svgalib_setup_VGA_registers(moderegs, modetiming, modeinfo); in r128_initializemode() 885 R128Init(modetiming, modeinfo, (R128SavePtr)(moderegs+VGA_TOTAL_REGS)); in r128_initializemode() 893 unsigned char *moderegs; in r128_setmode() local 912 moderegs = malloc(R128_TOTAL_REGS); in r128_setmode() 914 r128_initializemode(moderegs, modetiming, modeinfo, mode); in r128_setmode() 917 __svgalib_setregs(moderegs); /* Set standard regs. */ in r128_setmode() 918 r128_setregs(moderegs, mode); /* Set extended regs. */ in r128_setmode() 919 free(moderegs); in r128_setmode()
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H A D | vgaregs.h | 103 unsigned char *moderegs,
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/dports/misc/rump/buildrump.sh-b914579/src/sys/dev/ic/ |
H A D | vga_raster.c | 1468 struct vga_moderegs moderegs; in vga_raster_setscreentype() local 1470 vga_setup_regs((struct videomode *)type->modecookie, &moderegs); in vga_raster_setscreentype() 1471 vga_set_mode(vh, &moderegs); in vga_raster_setscreentype()
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