/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/Mips/ |
H A D | madd-msub.ll | 22 ; 32-DAG: mtlo $6 28 ; DSP-DAG: mtlo $6, $[[AC:ac[0-3]+]] 68 ; 32-DAG: mtlo $6 74 ; DSP-DAG: mtlo $6, $[[AC:ac[0-3]+]] 106 ; 32-DAG: mtlo $7 112 ; DSP-DAG: mtlo $7, $[[AC]] 158 ; 32-DAG: mtlo $6 164 ; DSP-DAG: mtlo $6, $[[AC:ac[0-3]+]] 204 ; 32-DAG: mtlo $6 210 ; DSP-DAG: mtlo $6, $[[AC:ac[0-3]+]] [all …]
|
H A D | inlineasm-cnstrnt-reg.ll | 36 ; CHECK: mtlo ${{[0-9]+}} 41 …call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounw… 46 ; CHECK: mtlo ${{[0-9]+}} 51 …call i16 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounw…
|
/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/Mips/ |
H A D | madd-msub.ll | 15 ; 32-DAG: mtlo $6 21 ; DSP-DAG: mtlo $6, $[[AC:ac[0-3]+]] 61 ; 32-DAG: mtlo $6 67 ; DSP-DAG: mtlo $6, $[[AC:ac[0-3]+]] 99 ; 32-DAG: mtlo $7 105 ; DSP-DAG: mtlo $7, $[[AC]] 151 ; 32-DAG: mtlo $6 157 ; DSP-DAG: mtlo $6, $[[AC:ac[0-3]+]] 197 ; 32-DAG: mtlo $6 203 ; DSP-DAG: mtlo $6, $[[AC:ac[0-3]+]] [all …]
|
H A D | inlineasm-cnstrnt-reg.ll | 36 ; CHECK: mtlo ${{[0-9]+}} 41 …call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounw… 46 ; CHECK: mtlo ${{[0-9]+}} 51 …call i16 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounw…
|
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/Mips/ |
H A D | inlineasm-constraint-reg.ll | 36 ; CHECK: mtlo ${{[0-9]+}} 41 …call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounw… 46 ; CHECK: mtlo ${{[0-9]+}} 51 …call i16 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounw…
|
H A D | madd-msub.ll | 15 ; 32-NEXT: mtlo $6 36 ; DSP-NEXT: mtlo $6, $ac0 87 ; 32-NEXT: mtlo $6 106 ; DSP-NEXT: mtlo $6, $ac0 148 ; 32-NEXT: mtlo $7 167 ; DSP-NEXT: mtlo $7, $ac0 264 ; 32-NEXT: mtlo $6 285 ; DSP-NEXT: mtlo $6, $ac0 336 ; 32-NEXT: mtlo $6 356 ; DSP-NEXT: mtlo $6, $ac0 [all …]
|
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/Mips/ |
H A D | inlineasm-constraint-reg.ll | 36 ; CHECK: mtlo ${{[0-9]+}} 41 …call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounw… 46 ; CHECK: mtlo ${{[0-9]+}} 51 …call i16 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounw…
|
H A D | madd-msub.ll | 15 ; 32-NEXT: mtlo $6 36 ; DSP-NEXT: mtlo $6, $ac0 87 ; 32-NEXT: mtlo $6 106 ; DSP-NEXT: mtlo $6, $ac0 148 ; 32-NEXT: mtlo $7 167 ; DSP-NEXT: mtlo $7, $ac0 264 ; 32-NEXT: mtlo $6 285 ; DSP-NEXT: mtlo $6, $ac0 336 ; 32-NEXT: mtlo $6 356 ; DSP-NEXT: mtlo $6, $ac0 [all …]
|
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/Mips/ |
H A D | inlineasm-constraint-reg.ll | 36 ; CHECK: mtlo ${{[0-9]+}} 41 …call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounw… 46 ; CHECK: mtlo ${{[0-9]+}} 51 …call i16 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounw…
|
H A D | madd-msub.ll | 15 ; 32-NEXT: mtlo $6 36 ; DSP-NEXT: mtlo $6, $ac0 87 ; 32-NEXT: mtlo $6 106 ; DSP-NEXT: mtlo $6, $ac0 148 ; 32-NEXT: mtlo $7 167 ; DSP-NEXT: mtlo $7, $ac0 264 ; 32-NEXT: mtlo $6 285 ; DSP-NEXT: mtlo $6, $ac0 336 ; 32-NEXT: mtlo $6 356 ; DSP-NEXT: mtlo $6, $ac0 [all …]
|
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/Mips/ |
H A D | inlineasm-constraint-reg.ll | 36 ; CHECK: mtlo ${{[0-9]+}} 41 …call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounw… 46 ; CHECK: mtlo ${{[0-9]+}} 51 …call i16 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounw…
|
H A D | madd-msub.ll | 15 ; 32-NEXT: mtlo $6 36 ; DSP-NEXT: mtlo $6, $ac0 87 ; 32-NEXT: mtlo $6 106 ; DSP-NEXT: mtlo $6, $ac0 148 ; 32-NEXT: mtlo $7 167 ; DSP-NEXT: mtlo $7, $ac0 264 ; 32-NEXT: mtlo $6 285 ; DSP-NEXT: mtlo $6, $ac0 336 ; 32-NEXT: mtlo $6 356 ; DSP-NEXT: mtlo $6, $ac0 [all …]
|
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/Mips/ |
H A D | inlineasm-constraint-reg.ll | 36 ; CHECK: mtlo ${{[0-9]+}} 41 …call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounw… 46 ; CHECK: mtlo ${{[0-9]+}} 51 …call i16 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounw…
|
H A D | madd-msub.ll | 15 ; 32-NEXT: mtlo $6 36 ; DSP-NEXT: mtlo $6, $ac0 87 ; 32-NEXT: mtlo $6 106 ; DSP-NEXT: mtlo $6, $ac0 148 ; 32-NEXT: mtlo $7 167 ; DSP-NEXT: mtlo $7, $ac0 264 ; 32-NEXT: mtlo $6 285 ; DSP-NEXT: mtlo $6, $ac0 336 ; 32-NEXT: mtlo $6 356 ; DSP-NEXT: mtlo $6, $ac0 [all …]
|
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/Mips/ |
H A D | inlineasm-constraint-reg.ll | 36 ; CHECK: mtlo ${{[0-9]+}} 41 …call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounw… 46 ; CHECK: mtlo ${{[0-9]+}} 51 …call i16 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounw…
|
H A D | madd-msub.ll | 15 ; 32-NEXT: mtlo $6 36 ; DSP-NEXT: mtlo $6, $ac0 87 ; 32-NEXT: mtlo $6 106 ; DSP-NEXT: mtlo $6, $ac0 148 ; 32-NEXT: mtlo $7 167 ; DSP-NEXT: mtlo $7, $ac0 264 ; 32-NEXT: mtlo $6 285 ; DSP-NEXT: mtlo $6, $ac0 336 ; 32-NEXT: mtlo $6 356 ; DSP-NEXT: mtlo $6, $ac0 [all …]
|
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/Mips/ |
H A D | inlineasm-constraint-reg.ll | 36 ; CHECK: mtlo ${{[0-9]+}} 41 …call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounw… 46 ; CHECK: mtlo ${{[0-9]+}} 51 …call i16 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounw…
|
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/Mips/ |
H A D | inlineasm-constraint-reg.ll | 36 ; CHECK: mtlo ${{[0-9]+}} 41 …call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounw… 46 ; CHECK: mtlo ${{[0-9]+}} 51 …call i16 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounw…
|
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/Mips/ |
H A D | inlineasm-constraint-reg.ll | 36 ; CHECK: mtlo ${{[0-9]+}} 41 …call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounw… 46 ; CHECK: mtlo ${{[0-9]+}} 51 …call i16 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounw…
|
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/Mips/ |
H A D | inlineasm-constraint-reg.ll | 36 ; CHECK: mtlo ${{[0-9]+}} 41 …call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounw… 46 ; CHECK: mtlo ${{[0-9]+}} 51 …call i16 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounw…
|
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/Mips/ |
H A D | inlineasm-constraint-reg.ll | 36 ; CHECK: mtlo ${{[0-9]+}} 41 …call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounw… 46 ; CHECK: mtlo ${{[0-9]+}} 51 …call i16 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounw…
|
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/Mips/ |
H A D | inlineasm-constraint-reg.ll | 36 ; CHECK: mtlo ${{[0-9]+}} 41 …call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounw… 46 ; CHECK: mtlo ${{[0-9]+}} 51 …call i16 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounw…
|
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/Mips/ |
H A D | inlineasm-constraint-reg.ll | 36 ; CHECK: mtlo ${{[0-9]+}} 41 …call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounw… 46 ; CHECK: mtlo ${{[0-9]+}} 51 …call i16 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounw…
|
/dports/devel/avr-gdb/gdb-7.3.1/sim/testsuite/sim/mips/ |
H A D | utils-dsp.inc | 154 mtlo $4, $ac3 181 mtlo $4, $ac1 201 mtlo $4, \acc 228 mtlo $4, $ac1 249 mtlo $4, $ac2 270 mtlo $4, $ac2 287 mtlo $4, $ac2 309 mtlo $4, $ac2 327 mtlo $4, $ac0 351 mtlo $4, $ac0 [all …]
|
/dports/devel/gdb761/gdb-7.6.1/sim/testsuite/sim/mips/ |
H A D | utils-dsp.inc | 153 mtlo $4, $ac3 180 mtlo $4, $ac1 200 mtlo $4, \acc 227 mtlo $4, $ac1 248 mtlo $4, $ac2 269 mtlo $4, $ac2 286 mtlo $4, $ac2 308 mtlo $4, $ac2 326 mtlo $4, $ac0 350 mtlo $4, $ac0 [all …]
|