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Searched refs:mux_plld_out0_plld2_out0 (Results 1 – 6 of 6) sorted by relevance

/dports/multimedia/libv4l/linux-5.13-rc2/drivers/clk/tegra/
H A Dclk-tegra114.c617 static const char *mux_plld_out0_plld2_out0[] = { variable
1027 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0, in tegra114_periph_clk_init()
1028 ARRAY_SIZE(mux_plld_out0_plld2_out0), in tegra114_periph_clk_init()
1034 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0, in tegra114_periph_clk_init()
1035 ARRAY_SIZE(mux_plld_out0_plld2_out0), in tegra114_periph_clk_init()
H A Dclk-tegra30.c999 static const char *mux_plld_out0_plld2_out0[] = { "pll_d_out0", variable
1016 …TEGRA_INIT_DATA_NODIV("dsib", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, 0, TEGRA30_CLK…
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/clk/tegra/
H A Dclk-tegra114.c617 static const char *mux_plld_out0_plld2_out0[] = { variable
1027 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0, in tegra114_periph_clk_init()
1028 ARRAY_SIZE(mux_plld_out0_plld2_out0), in tegra114_periph_clk_init()
1034 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0, in tegra114_periph_clk_init()
1035 ARRAY_SIZE(mux_plld_out0_plld2_out0), in tegra114_periph_clk_init()
H A Dclk-tegra30.c999 static const char *mux_plld_out0_plld2_out0[] = { "pll_d_out0", variable
1016 …TEGRA_INIT_DATA_NODIV("dsib", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, 0, TEGRA30_CLK…
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/clk/tegra/
H A Dclk-tegra114.c617 static const char *mux_plld_out0_plld2_out0[] = { variable
1027 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0, in tegra114_periph_clk_init()
1028 ARRAY_SIZE(mux_plld_out0_plld2_out0), in tegra114_periph_clk_init()
1034 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0, in tegra114_periph_clk_init()
1035 ARRAY_SIZE(mux_plld_out0_plld2_out0), in tegra114_periph_clk_init()
H A Dclk-tegra30.c999 static const char *mux_plld_out0_plld2_out0[] = { "pll_d_out0", variable
1016 …TEGRA_INIT_DATA_NODIV("dsib", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, 0, TEGRA30_CLK…