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/dports/emulators/qemu5/qemu-5.2.0/tests/tcg/i386/
H A Dtest-i386-sse-exceptions.c54 uint32_t mxcsr; in main() local
61 if ((mxcsr & EXC) != IE) { in main()
85 if ((mxcsr & EXC) != PE) { in main()
93 if ((mxcsr & EXC) != IE) { in main()
101 if ((mxcsr & EXC) != PE) { in main()
108 if ((mxcsr & EXC) != 0) { in main()
115 if ((mxcsr & EXC) != IE) { in main()
122 if ((mxcsr & EXC) != IE) { in main()
137 if ((mxcsr & EXC) != 0) { in main()
166 if ((mxcsr & EXC) != 0) { in main()
[all …]
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/tests/tcg/i386/
H A Dtest-i386-sse-exceptions.c54 uint32_t mxcsr;
61 if ((mxcsr & EXC) != IE) {
85 if ((mxcsr & EXC) != PE) {
93 if ((mxcsr & EXC) != IE) {
101 if ((mxcsr & EXC) != PE) {
108 if ((mxcsr & EXC) != 0) {
115 if ((mxcsr & EXC) != IE) {
122 if ((mxcsr & EXC) != IE) {
137 if ((mxcsr & EXC) != 0) {
166 if ((mxcsr & EXC) != 0) {
[all …]
/dports/emulators/qemu/qemu-6.2.0/tests/tcg/i386/
H A Dtest-i386-sse-exceptions.c54 uint32_t mxcsr; in main() local
61 if ((mxcsr & EXC) != IE) { in main()
85 if ((mxcsr & EXC) != PE) { in main()
93 if ((mxcsr & EXC) != IE) { in main()
101 if ((mxcsr & EXC) != PE) { in main()
108 if ((mxcsr & EXC) != 0) { in main()
115 if ((mxcsr & EXC) != IE) { in main()
122 if ((mxcsr & EXC) != IE) { in main()
137 if ((mxcsr & EXC) != 0) { in main()
166 if ((mxcsr & EXC) != 0) { in main()
[all …]
/dports/emulators/qemu60/qemu-6.0.0/tests/tcg/i386/
H A Dtest-i386-sse-exceptions.c54 uint32_t mxcsr; in main() local
61 if ((mxcsr & EXC) != IE) { in main()
85 if ((mxcsr & EXC) != PE) { in main()
93 if ((mxcsr & EXC) != IE) { in main()
101 if ((mxcsr & EXC) != PE) { in main()
108 if ((mxcsr & EXC) != 0) { in main()
115 if ((mxcsr & EXC) != IE) { in main()
122 if ((mxcsr & EXC) != IE) { in main()
137 if ((mxcsr & EXC) != 0) { in main()
166 if ((mxcsr & EXC) != 0) { in main()
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/X86/
H A Devex-to-vex-compress.mir816 ; CHECK: $ymm0 = VCVTDQ2PSYrr $ymm0, implicit $mxcsr
817 $ymm0 = VCVTDQ2PSZ256rr $ymm0, implicit $mxcsr
820 ; CHECK: $xmm0 = VCVTPD2DQYrr $ymm0, implicit $mxcsr
821 $xmm0 = VCVTPD2DQZ256rr $ymm0, implicit $mxcsr
824 ; CHECK: $xmm0 = VCVTPD2PSYrr $ymm0, implicit $mxcsr
825 $xmm0 = VCVTPD2PSZ256rr $ymm0, implicit $mxcsr
828 ; CHECK: $ymm0 = VCVTPS2DQYrr $ymm0, implicit $mxcsr
829 $ymm0 = VCVTPS2DQZ256rr $ymm0, implicit $mxcsr
832 ; CHECK: $ymm0 = VCVTPS2PDYrr $xmm0, implicit $mxcsr
833 $ymm0 = VCVTPS2PDZ256rr $xmm0, implicit $mxcsr
[all …]
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/X86/
H A Devex-to-vex-compress.mir816 ; CHECK: $ymm0 = VCVTDQ2PSYrr $ymm0, implicit $mxcsr
817 $ymm0 = VCVTDQ2PSZ256rr $ymm0, implicit $mxcsr
820 ; CHECK: $xmm0 = VCVTPD2DQYrr $ymm0, implicit $mxcsr
821 $xmm0 = VCVTPD2DQZ256rr $ymm0, implicit $mxcsr
824 ; CHECK: $xmm0 = VCVTPD2PSYrr $ymm0, implicit $mxcsr
825 $xmm0 = VCVTPD2PSZ256rr $ymm0, implicit $mxcsr
828 ; CHECK: $ymm0 = VCVTPS2DQYrr $ymm0, implicit $mxcsr
829 $ymm0 = VCVTPS2DQZ256rr $ymm0, implicit $mxcsr
832 ; CHECK: $ymm0 = VCVTPS2PDYrr $xmm0, implicit $mxcsr
833 $ymm0 = VCVTPS2PDZ256rr $xmm0, implicit $mxcsr
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/X86/
H A Devex-to-vex-compress.mir816 ; CHECK: $ymm0 = VCVTDQ2PSYrr $ymm0, implicit $mxcsr
817 $ymm0 = VCVTDQ2PSZ256rr $ymm0, implicit $mxcsr
820 ; CHECK: $xmm0 = VCVTPD2DQYrr $ymm0, implicit $mxcsr
821 $xmm0 = VCVTPD2DQZ256rr $ymm0, implicit $mxcsr
824 ; CHECK: $xmm0 = VCVTPD2PSYrr $ymm0, implicit $mxcsr
825 $xmm0 = VCVTPD2PSZ256rr $ymm0, implicit $mxcsr
828 ; CHECK: $ymm0 = VCVTPS2DQYrr $ymm0, implicit $mxcsr
829 $ymm0 = VCVTPS2DQZ256rr $ymm0, implicit $mxcsr
832 ; CHECK: $ymm0 = VCVTPS2PDYrr $xmm0, implicit $mxcsr
833 $ymm0 = VCVTPS2PDZ256rr $xmm0, implicit $mxcsr
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/X86/
H A Devex-to-vex-compress.mir816 ; CHECK: $ymm0 = VCVTDQ2PSYrr $ymm0, implicit $mxcsr
817 $ymm0 = VCVTDQ2PSZ256rr $ymm0, implicit $mxcsr
820 ; CHECK: $xmm0 = VCVTPD2DQYrr $ymm0, implicit $mxcsr
821 $xmm0 = VCVTPD2DQZ256rr $ymm0, implicit $mxcsr
824 ; CHECK: $xmm0 = VCVTPD2PSYrr $ymm0, implicit $mxcsr
825 $xmm0 = VCVTPD2PSZ256rr $ymm0, implicit $mxcsr
828 ; CHECK: $ymm0 = VCVTPS2DQYrr $ymm0, implicit $mxcsr
829 $ymm0 = VCVTPS2DQZ256rr $ymm0, implicit $mxcsr
832 ; CHECK: $ymm0 = VCVTPS2PDYrr $xmm0, implicit $mxcsr
833 $ymm0 = VCVTPS2PDZ256rr $xmm0, implicit $mxcsr
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/X86/
H A Devex-to-vex-compress.mir816 ; CHECK: $ymm0 = VCVTDQ2PSYrr $ymm0, implicit $mxcsr
817 $ymm0 = VCVTDQ2PSZ256rr $ymm0, implicit $mxcsr
820 ; CHECK: $xmm0 = VCVTPD2DQYrr $ymm0, implicit $mxcsr
821 $xmm0 = VCVTPD2DQZ256rr $ymm0, implicit $mxcsr
824 ; CHECK: $xmm0 = VCVTPD2PSYrr $ymm0, implicit $mxcsr
825 $xmm0 = VCVTPD2PSZ256rr $ymm0, implicit $mxcsr
828 ; CHECK: $ymm0 = VCVTPS2DQYrr $ymm0, implicit $mxcsr
829 $ymm0 = VCVTPS2DQZ256rr $ymm0, implicit $mxcsr
832 ; CHECK: $ymm0 = VCVTPS2PDYrr $xmm0, implicit $mxcsr
833 $ymm0 = VCVTPS2PDZ256rr $xmm0, implicit $mxcsr
[all …]
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/test/CodeGen/X86/
H A Devex-to-vex-compress.mir816 ; CHECK: $ymm0 = VCVTDQ2PSYrr $ymm0, implicit $mxcsr
817 $ymm0 = VCVTDQ2PSZ256rr $ymm0, implicit $mxcsr
820 ; CHECK: $xmm0 = VCVTPD2DQYrr $ymm0, implicit $mxcsr
821 $xmm0 = VCVTPD2DQZ256rr $ymm0, implicit $mxcsr
824 ; CHECK: $xmm0 = VCVTPD2PSYrr $ymm0, implicit $mxcsr
825 $xmm0 = VCVTPD2PSZ256rr $ymm0, implicit $mxcsr
828 ; CHECK: $ymm0 = VCVTPS2DQYrr $ymm0, implicit $mxcsr
829 $ymm0 = VCVTPS2DQZ256rr $ymm0, implicit $mxcsr
832 ; CHECK: $ymm0 = VCVTPS2PDYrr $xmm0, implicit $mxcsr
833 $ymm0 = VCVTPS2PDZ256rr $xmm0, implicit $mxcsr
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/X86/
H A Devex-to-vex-compress.mir816 ; CHECK: $ymm0 = VCVTDQ2PSYrr $ymm0, implicit $mxcsr
817 $ymm0 = VCVTDQ2PSZ256rr $ymm0, implicit $mxcsr
820 ; CHECK: $xmm0 = VCVTPD2DQYrr $ymm0, implicit $mxcsr
821 $xmm0 = VCVTPD2DQZ256rr $ymm0, implicit $mxcsr
824 ; CHECK: $xmm0 = VCVTPD2PSYrr $ymm0, implicit $mxcsr
825 $xmm0 = VCVTPD2PSZ256rr $ymm0, implicit $mxcsr
828 ; CHECK: $ymm0 = VCVTPS2DQYrr $ymm0, implicit $mxcsr
829 $ymm0 = VCVTPS2DQZ256rr $ymm0, implicit $mxcsr
832 ; CHECK: $ymm0 = VCVTPS2PDYrr $xmm0, implicit $mxcsr
833 $ymm0 = VCVTPS2PDZ256rr $xmm0, implicit $mxcsr
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/X86/
H A Devex-to-vex-compress.mir816 ; CHECK: $ymm0 = VCVTDQ2PSYrr $ymm0, implicit $mxcsr
817 $ymm0 = VCVTDQ2PSZ256rr $ymm0, implicit $mxcsr
820 ; CHECK: $xmm0 = VCVTPD2DQYrr $ymm0, implicit $mxcsr
821 $xmm0 = VCVTPD2DQZ256rr $ymm0, implicit $mxcsr
824 ; CHECK: $xmm0 = VCVTPD2PSYrr $ymm0, implicit $mxcsr
825 $xmm0 = VCVTPD2PSZ256rr $ymm0, implicit $mxcsr
828 ; CHECK: $ymm0 = VCVTPS2DQYrr $ymm0, implicit $mxcsr
829 $ymm0 = VCVTPS2DQZ256rr $ymm0, implicit $mxcsr
832 ; CHECK: $ymm0 = VCVTPS2PDYrr $xmm0, implicit $mxcsr
833 $ymm0 = VCVTPS2PDZ256rr $xmm0, implicit $mxcsr
[all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/X86/
H A Devex-to-vex-compress.mir816 ; CHECK: $ymm0 = VCVTDQ2PSYrr $ymm0, implicit $mxcsr
817 $ymm0 = VCVTDQ2PSZ256rr $ymm0, implicit $mxcsr
820 ; CHECK: $xmm0 = VCVTPD2DQYrr $ymm0, implicit $mxcsr
821 $xmm0 = VCVTPD2DQZ256rr $ymm0, implicit $mxcsr
824 ; CHECK: $xmm0 = VCVTPD2PSYrr $ymm0, implicit $mxcsr
825 $xmm0 = VCVTPD2PSZ256rr $ymm0, implicit $mxcsr
828 ; CHECK: $ymm0 = VCVTPS2DQYrr $ymm0, implicit $mxcsr
829 $ymm0 = VCVTPS2DQZ256rr $ymm0, implicit $mxcsr
832 ; CHECK: $ymm0 = VCVTPS2PDYrr $xmm0, implicit $mxcsr
833 $ymm0 = VCVTPS2PDZ256rr $xmm0, implicit $mxcsr
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/X86/
H A Devex-to-vex-compress.mir816 ; CHECK: $ymm0 = VCVTDQ2PSYrr $ymm0, implicit $mxcsr
817 $ymm0 = VCVTDQ2PSZ256rr $ymm0, implicit $mxcsr
820 ; CHECK: $xmm0 = VCVTPD2DQYrr $ymm0, implicit $mxcsr
821 $xmm0 = VCVTPD2DQZ256rr $ymm0, implicit $mxcsr
824 ; CHECK: $xmm0 = VCVTPD2PSYrr $ymm0, implicit $mxcsr
825 $xmm0 = VCVTPD2PSZ256rr $ymm0, implicit $mxcsr
828 ; CHECK: $ymm0 = VCVTPS2DQYrr $ymm0, implicit $mxcsr
829 $ymm0 = VCVTPS2DQZ256rr $ymm0, implicit $mxcsr
832 ; CHECK: $ymm0 = VCVTPS2PDYrr $xmm0, implicit $mxcsr
833 $ymm0 = VCVTPS2PDZ256rr $xmm0, implicit $mxcsr
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/X86/
H A Devex-to-vex-compress.mir816 ; CHECK: $ymm0 = VCVTDQ2PSYrr $ymm0, implicit $mxcsr
817 $ymm0 = VCVTDQ2PSZ256rr $ymm0, implicit $mxcsr
820 ; CHECK: $xmm0 = VCVTPD2DQYrr $ymm0, implicit $mxcsr
821 $xmm0 = VCVTPD2DQZ256rr $ymm0, implicit $mxcsr
824 ; CHECK: $xmm0 = VCVTPD2PSYrr $ymm0, implicit $mxcsr
825 $xmm0 = VCVTPD2PSZ256rr $ymm0, implicit $mxcsr
828 ; CHECK: $ymm0 = VCVTPS2DQYrr $ymm0, implicit $mxcsr
829 $ymm0 = VCVTPS2DQZ256rr $ymm0, implicit $mxcsr
832 ; CHECK: $ymm0 = VCVTPS2PDYrr $xmm0, implicit $mxcsr
833 $ymm0 = VCVTPS2PDZ256rr $xmm0, implicit $mxcsr
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/X86/
H A Devex-to-vex-compress.mir816 ; CHECK: $ymm0 = VCVTDQ2PSYrr $ymm0, implicit $mxcsr
817 $ymm0 = VCVTDQ2PSZ256rr $ymm0, implicit $mxcsr
820 ; CHECK: $xmm0 = VCVTPD2DQYrr $ymm0, implicit $mxcsr
821 $xmm0 = VCVTPD2DQZ256rr $ymm0, implicit $mxcsr
824 ; CHECK: $xmm0 = VCVTPD2PSYrr $ymm0, implicit $mxcsr
825 $xmm0 = VCVTPD2PSZ256rr $ymm0, implicit $mxcsr
828 ; CHECK: $ymm0 = VCVTPS2DQYrr $ymm0, implicit $mxcsr
829 $ymm0 = VCVTPS2DQZ256rr $ymm0, implicit $mxcsr
832 ; CHECK: $ymm0 = VCVTPS2PDYrr $xmm0, implicit $mxcsr
833 $ymm0 = VCVTPS2PDZ256rr $xmm0, implicit $mxcsr
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/X86/
H A Devex-to-vex-compress.mir816 ; CHECK: $ymm0 = VCVTDQ2PSYrr $ymm0, implicit $mxcsr
817 $ymm0 = VCVTDQ2PSZ256rr $ymm0, implicit $mxcsr
820 ; CHECK: $xmm0 = VCVTPD2DQYrr $ymm0, implicit $mxcsr
821 $xmm0 = VCVTPD2DQZ256rr $ymm0, implicit $mxcsr
824 ; CHECK: $xmm0 = VCVTPD2PSYrr $ymm0, implicit $mxcsr
825 $xmm0 = VCVTPD2PSZ256rr $ymm0, implicit $mxcsr
828 ; CHECK: $ymm0 = VCVTPS2DQYrr $ymm0, implicit $mxcsr
829 $ymm0 = VCVTPS2DQZ256rr $ymm0, implicit $mxcsr
832 ; CHECK: $ymm0 = VCVTPS2PDYrr $xmm0, implicit $mxcsr
833 $ymm0 = VCVTPS2PDZ256rr $xmm0, implicit $mxcsr
[all …]
/dports/math/openlibm/openlibm-0.8.0/i387/
H A Dfenv.c100 uint32_t mxcsr; in fesetexceptflag() local
111 __ldmxcsr(mxcsr); in fesetexceptflag()
134 uint32_t mxcsr; in fegetenv() local
152 uint32_t mxcsr; in feholdexcept() local
161 __ldmxcsr(mxcsr); in feholdexcept()
171 uint32_t mxcsr; in feupdateenv() local
178 mxcsr = 0; in feupdateenv()
195 mxcsr = 0; in feenableexcept()
201 __ldmxcsr(mxcsr); in feenableexcept()
217 mxcsr = 0; in fedisableexcept()
[all …]
/dports/devel/tinygo/tinygo-0.14.1/lib/picolibc/newlib/libm/machine/i386/
H A Dfenv.c79 unsigned int mxcsr = 0; in feenableexcept() local
115 unsigned int mxcsr = 0; in fedisableexcept() local
179 unsigned int mxcsr; in feholdexcept() local
181 mxcsr = envp->_sse_mxcsr & ~FE_ALL_EXCEPT; in feholdexcept()
216 unsigned int mxcsr = 0; in feupdateenv() local
290 unsigned int mxcsr = 0; in fetestexcept() local
301 return (sw | mxcsr) & excepts; in fetestexcept()
311 unsigned int mxcsr = 0; in fegetexceptflag() local
322 *flagp = (sw | mxcsr) & excepts; in fegetexceptflag()
371 unsigned int mxcsr = 0; in fesetround() local
[all …]
/dports/devel/tinygo/tinygo-0.14.1/lib/picolibc/newlib/libm/machine/x86_64/
H A Dfenv.c79 unsigned int mxcsr = 0; in feenableexcept() local
115 unsigned int mxcsr = 0; in fedisableexcept() local
179 unsigned int mxcsr; in feholdexcept() local
181 mxcsr = envp->_sse_mxcsr & ~FE_ALL_EXCEPT; in feholdexcept()
216 unsigned int mxcsr = 0; in feupdateenv() local
290 unsigned int mxcsr = 0; in fetestexcept() local
301 return (sw | mxcsr) & excepts; in fetestexcept()
311 unsigned int mxcsr = 0; in fegetexceptflag() local
322 *flagp = (sw | mxcsr) & excepts; in fegetexceptflag()
371 unsigned int mxcsr = 0; in fesetround() local
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/MIR/X86/
H A Dfastmath.mir13 ; CHECK: %1:fr32 = nnan VMULSSrr %0, %0, implicit $mxcsr
14 %1:fr32 = nnan VMULSSrr %0, %0, implicit $mxcsr
15 ; CHECK: %2:fr32 = ninf VMULSSrr %1, %1, implicit $mxcsr
16 %2:fr32 = ninf VMULSSrr %1, %1, implicit $mxcsr
17 ; CHECK: %3:fr32 = nsz VMULSSrr %2, %2, implicit $mxcsr
18 %3:fr32 = nsz VMULSSrr %2, %2, implicit $mxcsr
19 ; CHECK: %4:fr32 = arcp VMULSSrr %3, %3, implicit $mxcsr
20 %4:fr32 = arcp VMULSSrr %3, %3, implicit $mxcsr
22 %5:fr32 = contract VMULSSrr %4, %4, implicit $mxcsr
24 %6:fr32 = afn VMULSSrr %5, %5, implicit $mxcsr
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/MIR/X86/
H A Dfastmath.mir13 ; CHECK: %1:fr32 = nnan VMULSSrr %0, %0, implicit $mxcsr
14 %1:fr32 = nnan VMULSSrr %0, %0, implicit $mxcsr
15 ; CHECK: %2:fr32 = ninf VMULSSrr %1, %1, implicit $mxcsr
16 %2:fr32 = ninf VMULSSrr %1, %1, implicit $mxcsr
17 ; CHECK: %3:fr32 = nsz VMULSSrr %2, %2, implicit $mxcsr
18 %3:fr32 = nsz VMULSSrr %2, %2, implicit $mxcsr
19 ; CHECK: %4:fr32 = arcp VMULSSrr %3, %3, implicit $mxcsr
20 %4:fr32 = arcp VMULSSrr %3, %3, implicit $mxcsr
22 %5:fr32 = contract VMULSSrr %4, %4, implicit $mxcsr
24 %6:fr32 = afn VMULSSrr %5, %5, implicit $mxcsr
[all …]
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/MIR/X86/
H A Dfastmath.mir13 ; CHECK: %1:fr32 = nnan VMULSSrr %0, %0, implicit $mxcsr
14 %1:fr32 = nnan VMULSSrr %0, %0, implicit $mxcsr
15 ; CHECK: %2:fr32 = ninf VMULSSrr %1, %1, implicit $mxcsr
16 %2:fr32 = ninf VMULSSrr %1, %1, implicit $mxcsr
17 ; CHECK: %3:fr32 = nsz VMULSSrr %2, %2, implicit $mxcsr
18 %3:fr32 = nsz VMULSSrr %2, %2, implicit $mxcsr
19 ; CHECK: %4:fr32 = arcp VMULSSrr %3, %3, implicit $mxcsr
20 %4:fr32 = arcp VMULSSrr %3, %3, implicit $mxcsr
22 %5:fr32 = contract VMULSSrr %4, %4, implicit $mxcsr
24 %6:fr32 = afn VMULSSrr %5, %5, implicit $mxcsr
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/MIR/X86/
H A Dfastmath.mir13 ; CHECK: %1:fr32 = nnan VMULSSrr %0, %0, implicit $mxcsr
14 %1:fr32 = nnan VMULSSrr %0, %0, implicit $mxcsr
15 ; CHECK: %2:fr32 = ninf VMULSSrr %1, %1, implicit $mxcsr
16 %2:fr32 = ninf VMULSSrr %1, %1, implicit $mxcsr
17 ; CHECK: %3:fr32 = nsz VMULSSrr %2, %2, implicit $mxcsr
18 %3:fr32 = nsz VMULSSrr %2, %2, implicit $mxcsr
19 ; CHECK: %4:fr32 = arcp VMULSSrr %3, %3, implicit $mxcsr
20 %4:fr32 = arcp VMULSSrr %3, %3, implicit $mxcsr
22 %5:fr32 = contract VMULSSrr %4, %4, implicit $mxcsr
24 %6:fr32 = afn VMULSSrr %5, %5, implicit $mxcsr
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/MIR/X86/
H A Dfastmath.mir13 ; CHECK: %1:fr32 = nnan VMULSSrr %0, %0, implicit $mxcsr
14 %1:fr32 = nnan VMULSSrr %0, %0, implicit $mxcsr
15 ; CHECK: %2:fr32 = ninf VMULSSrr %1, %1, implicit $mxcsr
16 %2:fr32 = ninf VMULSSrr %1, %1, implicit $mxcsr
17 ; CHECK: %3:fr32 = nsz VMULSSrr %2, %2, implicit $mxcsr
18 %3:fr32 = nsz VMULSSrr %2, %2, implicit $mxcsr
19 ; CHECK: %4:fr32 = arcp VMULSSrr %3, %3, implicit $mxcsr
20 %4:fr32 = arcp VMULSSrr %3, %3, implicit $mxcsr
22 %5:fr32 = contract VMULSSrr %4, %4, implicit $mxcsr
24 %6:fr32 = afn VMULSSrr %5, %5, implicit $mxcsr
[all …]

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