| /dports/lang/clover/mesa-21.3.6/src/amd/common/ |
| H A D | ac_nir_lower_tess_io_to_mem.c | 219 nir_ssa_def *base_off_var = nir_imul_imm(b, vertex_idx, st->tcs_num_reserved_inputs * 16u); in lower_ls_output_store()
275 nir_ssa_def *tcs_in_patch_stride = nir_imul_imm(b, tcs_in_vtxcnt, tcs_in_vertex_stride); in hs_per_vertex_input_lds_offset()
279 nir_ssa_def *vertex_index_off = nir_imul_imm(b, vertex_index, tcs_in_vertex_stride); in hs_per_vertex_input_lds_offset()
301 … nir_ssa_def *input_patch_size = nir_imul_imm(b, tcs_in_vtxcnt, st->tcs_num_reserved_inputs * 16u); in hs_output_lds_offset()
309 nir_ssa_def *patch_offset = nir_imul_imm(b, rel_patch_id, output_patch_stride); in hs_output_lds_offset()
314 nir_ssa_def *vertex_index_off = nir_imul_imm(b, vertex_index, output_vertex_size); in hs_output_lds_offset()
338 …nir_ssa_def *patch_offset = nir_imul(b, rel_patch_id, nir_imul_imm(b, out_vertices_per_patch, 16u)… in hs_per_vertex_output_vmem_offset()
341 nir_ssa_def *vertex_index_off = nir_imul_imm(b, vertex_index, 16u); in hs_per_vertex_output_vmem_offset()
361 ? nir_build_calc_io_offset(b, intrin, nir_imul_imm(b, tcs_num_patches, 16u), 4u) in hs_per_patch_output_vmem_offset()
365 off = nir_iadd_nuw(b, off, nir_imul_imm(b, tcs_num_patches, const_base_offset)); in hs_per_patch_output_vmem_offset()
[all …]
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| /dports/graphics/libosmesa-gallium/mesa-21.3.6/src/amd/common/ |
| H A D | ac_nir_lower_tess_io_to_mem.c | 219 nir_ssa_def *base_off_var = nir_imul_imm(b, vertex_idx, st->tcs_num_reserved_inputs * 16u); in lower_ls_output_store()
275 nir_ssa_def *tcs_in_patch_stride = nir_imul_imm(b, tcs_in_vtxcnt, tcs_in_vertex_stride); in hs_per_vertex_input_lds_offset()
279 nir_ssa_def *vertex_index_off = nir_imul_imm(b, vertex_index, tcs_in_vertex_stride); in hs_per_vertex_input_lds_offset()
301 … nir_ssa_def *input_patch_size = nir_imul_imm(b, tcs_in_vtxcnt, st->tcs_num_reserved_inputs * 16u); in hs_output_lds_offset()
309 nir_ssa_def *patch_offset = nir_imul_imm(b, rel_patch_id, output_patch_stride); in hs_output_lds_offset()
314 nir_ssa_def *vertex_index_off = nir_imul_imm(b, vertex_index, output_vertex_size); in hs_output_lds_offset()
338 …nir_ssa_def *patch_offset = nir_imul(b, rel_patch_id, nir_imul_imm(b, out_vertices_per_patch, 16u)… in hs_per_vertex_output_vmem_offset()
341 nir_ssa_def *vertex_index_off = nir_imul_imm(b, vertex_index, 16u); in hs_per_vertex_output_vmem_offset()
361 ? nir_build_calc_io_offset(b, intrin, nir_imul_imm(b, tcs_num_patches, 16u), 4u) in hs_per_patch_output_vmem_offset()
365 off = nir_iadd_nuw(b, off, nir_imul_imm(b, tcs_num_patches, const_base_offset)); in hs_per_patch_output_vmem_offset()
[all …]
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| /dports/graphics/libosmesa/mesa-21.3.6/src/amd/common/ |
| H A D | ac_nir_lower_tess_io_to_mem.c | 219 nir_ssa_def *base_off_var = nir_imul_imm(b, vertex_idx, st->tcs_num_reserved_inputs * 16u); in lower_ls_output_store()
275 nir_ssa_def *tcs_in_patch_stride = nir_imul_imm(b, tcs_in_vtxcnt, tcs_in_vertex_stride); in hs_per_vertex_input_lds_offset()
279 nir_ssa_def *vertex_index_off = nir_imul_imm(b, vertex_index, tcs_in_vertex_stride); in hs_per_vertex_input_lds_offset()
301 … nir_ssa_def *input_patch_size = nir_imul_imm(b, tcs_in_vtxcnt, st->tcs_num_reserved_inputs * 16u); in hs_output_lds_offset()
309 nir_ssa_def *patch_offset = nir_imul_imm(b, rel_patch_id, output_patch_stride); in hs_output_lds_offset()
314 nir_ssa_def *vertex_index_off = nir_imul_imm(b, vertex_index, output_vertex_size); in hs_output_lds_offset()
338 …nir_ssa_def *patch_offset = nir_imul(b, rel_patch_id, nir_imul_imm(b, out_vertices_per_patch, 16u)… in hs_per_vertex_output_vmem_offset()
341 nir_ssa_def *vertex_index_off = nir_imul_imm(b, vertex_index, 16u); in hs_per_vertex_output_vmem_offset()
361 ? nir_build_calc_io_offset(b, intrin, nir_imul_imm(b, tcs_num_patches, 16u), 4u) in hs_per_patch_output_vmem_offset()
365 off = nir_iadd_nuw(b, off, nir_imul_imm(b, tcs_num_patches, const_base_offset)); in hs_per_patch_output_vmem_offset()
[all …]
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| /dports/graphics/mesa-libs/mesa-21.3.6/src/amd/common/ |
| H A D | ac_nir_lower_tess_io_to_mem.c | 219 nir_ssa_def *base_off_var = nir_imul_imm(b, vertex_idx, st->tcs_num_reserved_inputs * 16u); in lower_ls_output_store()
275 nir_ssa_def *tcs_in_patch_stride = nir_imul_imm(b, tcs_in_vtxcnt, tcs_in_vertex_stride); in hs_per_vertex_input_lds_offset()
279 nir_ssa_def *vertex_index_off = nir_imul_imm(b, vertex_index, tcs_in_vertex_stride); in hs_per_vertex_input_lds_offset()
301 … nir_ssa_def *input_patch_size = nir_imul_imm(b, tcs_in_vtxcnt, st->tcs_num_reserved_inputs * 16u); in hs_output_lds_offset()
309 nir_ssa_def *patch_offset = nir_imul_imm(b, rel_patch_id, output_patch_stride); in hs_output_lds_offset()
314 nir_ssa_def *vertex_index_off = nir_imul_imm(b, vertex_index, output_vertex_size); in hs_output_lds_offset()
338 …nir_ssa_def *patch_offset = nir_imul(b, rel_patch_id, nir_imul_imm(b, out_vertices_per_patch, 16u)… in hs_per_vertex_output_vmem_offset()
341 nir_ssa_def *vertex_index_off = nir_imul_imm(b, vertex_index, 16u); in hs_per_vertex_output_vmem_offset()
361 ? nir_build_calc_io_offset(b, intrin, nir_imul_imm(b, tcs_num_patches, 16u), 4u) in hs_per_patch_output_vmem_offset()
365 off = nir_iadd_nuw(b, off, nir_imul_imm(b, tcs_num_patches, const_base_offset)); in hs_per_patch_output_vmem_offset()
[all …]
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| /dports/graphics/mesa-gallium-va/mesa-21.3.6/src/amd/common/ |
| H A D | ac_nir_lower_tess_io_to_mem.c | 219 nir_ssa_def *base_off_var = nir_imul_imm(b, vertex_idx, st->tcs_num_reserved_inputs * 16u); in lower_ls_output_store()
275 nir_ssa_def *tcs_in_patch_stride = nir_imul_imm(b, tcs_in_vtxcnt, tcs_in_vertex_stride); in hs_per_vertex_input_lds_offset()
279 nir_ssa_def *vertex_index_off = nir_imul_imm(b, vertex_index, tcs_in_vertex_stride); in hs_per_vertex_input_lds_offset()
301 … nir_ssa_def *input_patch_size = nir_imul_imm(b, tcs_in_vtxcnt, st->tcs_num_reserved_inputs * 16u); in hs_output_lds_offset()
309 nir_ssa_def *patch_offset = nir_imul_imm(b, rel_patch_id, output_patch_stride); in hs_output_lds_offset()
314 nir_ssa_def *vertex_index_off = nir_imul_imm(b, vertex_index, output_vertex_size); in hs_output_lds_offset()
338 …nir_ssa_def *patch_offset = nir_imul(b, rel_patch_id, nir_imul_imm(b, out_vertices_per_patch, 16u)… in hs_per_vertex_output_vmem_offset()
341 nir_ssa_def *vertex_index_off = nir_imul_imm(b, vertex_index, 16u); in hs_per_vertex_output_vmem_offset()
361 ? nir_build_calc_io_offset(b, intrin, nir_imul_imm(b, tcs_num_patches, 16u), 4u) in hs_per_patch_output_vmem_offset()
365 off = nir_iadd_nuw(b, off, nir_imul_imm(b, tcs_num_patches, const_base_offset)); in hs_per_patch_output_vmem_offset()
[all …]
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| /dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/amd/common/ |
| H A D | ac_nir_lower_tess_io_to_mem.c | 219 nir_ssa_def *base_off_var = nir_imul_imm(b, vertex_idx, st->tcs_num_reserved_inputs * 16u); in lower_ls_output_store()
275 nir_ssa_def *tcs_in_patch_stride = nir_imul_imm(b, tcs_in_vtxcnt, tcs_in_vertex_stride); in hs_per_vertex_input_lds_offset()
279 nir_ssa_def *vertex_index_off = nir_imul_imm(b, vertex_index, tcs_in_vertex_stride); in hs_per_vertex_input_lds_offset()
301 … nir_ssa_def *input_patch_size = nir_imul_imm(b, tcs_in_vtxcnt, st->tcs_num_reserved_inputs * 16u); in hs_output_lds_offset()
309 nir_ssa_def *patch_offset = nir_imul_imm(b, rel_patch_id, output_patch_stride); in hs_output_lds_offset()
314 nir_ssa_def *vertex_index_off = nir_imul_imm(b, vertex_index, output_vertex_size); in hs_output_lds_offset()
338 …nir_ssa_def *patch_offset = nir_imul(b, rel_patch_id, nir_imul_imm(b, out_vertices_per_patch, 16u)… in hs_per_vertex_output_vmem_offset()
341 nir_ssa_def *vertex_index_off = nir_imul_imm(b, vertex_index, 16u); in hs_per_vertex_output_vmem_offset()
361 ? nir_build_calc_io_offset(b, intrin, nir_imul_imm(b, tcs_num_patches, 16u), 4u) in hs_per_patch_output_vmem_offset()
365 off = nir_iadd_nuw(b, off, nir_imul_imm(b, tcs_num_patches, const_base_offset)); in hs_per_patch_output_vmem_offset()
[all …]
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| /dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/amd/common/ |
| H A D | ac_nir_lower_tess_io_to_mem.c | 219 nir_ssa_def *base_off_var = nir_imul_imm(b, vertex_idx, st->tcs_num_reserved_inputs * 16u); in lower_ls_output_store()
275 nir_ssa_def *tcs_in_patch_stride = nir_imul_imm(b, tcs_in_vtxcnt, tcs_in_vertex_stride); in hs_per_vertex_input_lds_offset()
279 nir_ssa_def *vertex_index_off = nir_imul_imm(b, vertex_index, tcs_in_vertex_stride); in hs_per_vertex_input_lds_offset()
301 … nir_ssa_def *input_patch_size = nir_imul_imm(b, tcs_in_vtxcnt, st->tcs_num_reserved_inputs * 16u); in hs_output_lds_offset()
309 nir_ssa_def *patch_offset = nir_imul_imm(b, rel_patch_id, output_patch_stride); in hs_output_lds_offset()
314 nir_ssa_def *vertex_index_off = nir_imul_imm(b, vertex_index, output_vertex_size); in hs_output_lds_offset()
338 …nir_ssa_def *patch_offset = nir_imul(b, rel_patch_id, nir_imul_imm(b, out_vertices_per_patch, 16u)… in hs_per_vertex_output_vmem_offset()
341 nir_ssa_def *vertex_index_off = nir_imul_imm(b, vertex_index, 16u); in hs_per_vertex_output_vmem_offset()
361 ? nir_build_calc_io_offset(b, intrin, nir_imul_imm(b, tcs_num_patches, 16u), 4u) in hs_per_patch_output_vmem_offset()
365 off = nir_iadd_nuw(b, off, nir_imul_imm(b, tcs_num_patches, const_base_offset)); in hs_per_patch_output_vmem_offset()
[all …]
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| /dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/amd/common/ |
| H A D | ac_nir_lower_tess_io_to_mem.c | 219 nir_ssa_def *base_off_var = nir_imul_imm(b, vertex_idx, st->tcs_num_reserved_inputs * 16u); in lower_ls_output_store()
275 nir_ssa_def *tcs_in_patch_stride = nir_imul_imm(b, tcs_in_vtxcnt, tcs_in_vertex_stride); in hs_per_vertex_input_lds_offset()
279 nir_ssa_def *vertex_index_off = nir_imul_imm(b, vertex_index, tcs_in_vertex_stride); in hs_per_vertex_input_lds_offset()
301 … nir_ssa_def *input_patch_size = nir_imul_imm(b, tcs_in_vtxcnt, st->tcs_num_reserved_inputs * 16u); in hs_output_lds_offset()
309 nir_ssa_def *patch_offset = nir_imul_imm(b, rel_patch_id, output_patch_stride); in hs_output_lds_offset()
314 nir_ssa_def *vertex_index_off = nir_imul_imm(b, vertex_index, output_vertex_size); in hs_output_lds_offset()
338 …nir_ssa_def *patch_offset = nir_imul(b, rel_patch_id, nir_imul_imm(b, out_vertices_per_patch, 16u)… in hs_per_vertex_output_vmem_offset()
341 nir_ssa_def *vertex_index_off = nir_imul_imm(b, vertex_index, 16u); in hs_per_vertex_output_vmem_offset()
361 ? nir_build_calc_io_offset(b, intrin, nir_imul_imm(b, tcs_num_patches, 16u), 4u) in hs_per_patch_output_vmem_offset()
365 off = nir_iadd_nuw(b, off, nir_imul_imm(b, tcs_num_patches, const_base_offset)); in hs_per_patch_output_vmem_offset()
[all …]
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| /dports/graphics/mesa-dri/mesa-21.3.6/src/amd/common/ |
| H A D | ac_nir_lower_tess_io_to_mem.c | 219 nir_ssa_def *base_off_var = nir_imul_imm(b, vertex_idx, st->tcs_num_reserved_inputs * 16u); in lower_ls_output_store()
275 nir_ssa_def *tcs_in_patch_stride = nir_imul_imm(b, tcs_in_vtxcnt, tcs_in_vertex_stride); in hs_per_vertex_input_lds_offset()
279 nir_ssa_def *vertex_index_off = nir_imul_imm(b, vertex_index, tcs_in_vertex_stride); in hs_per_vertex_input_lds_offset()
301 … nir_ssa_def *input_patch_size = nir_imul_imm(b, tcs_in_vtxcnt, st->tcs_num_reserved_inputs * 16u); in hs_output_lds_offset()
309 nir_ssa_def *patch_offset = nir_imul_imm(b, rel_patch_id, output_patch_stride); in hs_output_lds_offset()
314 nir_ssa_def *vertex_index_off = nir_imul_imm(b, vertex_index, output_vertex_size); in hs_output_lds_offset()
338 …nir_ssa_def *patch_offset = nir_imul(b, rel_patch_id, nir_imul_imm(b, out_vertices_per_patch, 16u)… in hs_per_vertex_output_vmem_offset()
341 nir_ssa_def *vertex_index_off = nir_imul_imm(b, vertex_index, 16u); in hs_per_vertex_output_vmem_offset()
361 ? nir_build_calc_io_offset(b, intrin, nir_imul_imm(b, tcs_num_patches, 16u), 4u) in hs_per_patch_output_vmem_offset()
365 off = nir_iadd_nuw(b, off, nir_imul_imm(b, tcs_num_patches, const_base_offset)); in hs_per_patch_output_vmem_offset()
[all …]
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| /dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/amd/common/ |
| H A D | ac_nir_lower_tess_io_to_mem.c | 219 nir_ssa_def *base_off_var = nir_imul_imm(b, vertex_idx, st->tcs_num_reserved_inputs * 16u); in lower_ls_output_store()
275 nir_ssa_def *tcs_in_patch_stride = nir_imul_imm(b, tcs_in_vtxcnt, tcs_in_vertex_stride); in hs_per_vertex_input_lds_offset()
279 nir_ssa_def *vertex_index_off = nir_imul_imm(b, vertex_index, tcs_in_vertex_stride); in hs_per_vertex_input_lds_offset()
301 … nir_ssa_def *input_patch_size = nir_imul_imm(b, tcs_in_vtxcnt, st->tcs_num_reserved_inputs * 16u); in hs_output_lds_offset()
309 nir_ssa_def *patch_offset = nir_imul_imm(b, rel_patch_id, output_patch_stride); in hs_output_lds_offset()
314 nir_ssa_def *vertex_index_off = nir_imul_imm(b, vertex_index, output_vertex_size); in hs_output_lds_offset()
338 …nir_ssa_def *patch_offset = nir_imul(b, rel_patch_id, nir_imul_imm(b, out_vertices_per_patch, 16u)… in hs_per_vertex_output_vmem_offset()
341 nir_ssa_def *vertex_index_off = nir_imul_imm(b, vertex_index, 16u); in hs_per_vertex_output_vmem_offset()
361 ? nir_build_calc_io_offset(b, intrin, nir_imul_imm(b, tcs_num_patches, 16u), 4u) in hs_per_patch_output_vmem_offset()
365 off = nir_iadd_nuw(b, off, nir_imul_imm(b, tcs_num_patches, const_base_offset)); in hs_per_patch_output_vmem_offset()
[all …]
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| /dports/graphics/libosmesa-gallium/mesa-21.3.6/src/intel/compiler/ |
| H A D | brw_nir_lower_alpha_to_coverage.c | 75 return nir_ior(b, nir_imul_imm(b, part_a, 0x1111), in build_dither_mask()
76 nir_ior(b, nir_imul_imm(b, part_b, 0x0808), in build_dither_mask()
77 nir_imul_imm(b, part_c, 0x0100))); in build_dither_mask()
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| /dports/lang/clover/mesa-21.3.6/src/intel/compiler/ |
| H A D | brw_nir_lower_alpha_to_coverage.c | 75 return nir_ior(b, nir_imul_imm(b, part_a, 0x1111), in build_dither_mask()
76 nir_ior(b, nir_imul_imm(b, part_b, 0x0808), in build_dither_mask()
77 nir_imul_imm(b, part_c, 0x0100))); in build_dither_mask()
|
| /dports/graphics/libosmesa/mesa-21.3.6/src/intel/compiler/ |
| H A D | brw_nir_lower_alpha_to_coverage.c | 75 return nir_ior(b, nir_imul_imm(b, part_a, 0x1111), in build_dither_mask()
76 nir_ior(b, nir_imul_imm(b, part_b, 0x0808), in build_dither_mask()
77 nir_imul_imm(b, part_c, 0x0100))); in build_dither_mask()
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| /dports/graphics/mesa-libs/mesa-21.3.6/src/intel/compiler/ |
| H A D | brw_nir_lower_alpha_to_coverage.c | 75 return nir_ior(b, nir_imul_imm(b, part_a, 0x1111), in build_dither_mask()
76 nir_ior(b, nir_imul_imm(b, part_b, 0x0808), in build_dither_mask()
77 nir_imul_imm(b, part_c, 0x0100))); in build_dither_mask()
|
| /dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/intel/compiler/ |
| H A D | brw_nir_lower_alpha_to_coverage.c | 75 return nir_ior(b, nir_imul_imm(b, part_a, 0x1111), in build_dither_mask()
76 nir_ior(b, nir_imul_imm(b, part_b, 0x0808), in build_dither_mask()
77 nir_imul_imm(b, part_c, 0x0100))); in build_dither_mask()
|
| /dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/intel/compiler/ |
| H A D | brw_nir_lower_alpha_to_coverage.c | 75 return nir_ior(b, nir_imul_imm(b, part_a, 0x1111), in build_dither_mask()
76 nir_ior(b, nir_imul_imm(b, part_b, 0x0808), in build_dither_mask()
77 nir_imul_imm(b, part_c, 0x0100))); in build_dither_mask()
|
| /dports/graphics/mesa-gallium-va/mesa-21.3.6/src/intel/compiler/ |
| H A D | brw_nir_lower_alpha_to_coverage.c | 75 return nir_ior(b, nir_imul_imm(b, part_a, 0x1111), in build_dither_mask()
76 nir_ior(b, nir_imul_imm(b, part_b, 0x0808), in build_dither_mask()
77 nir_imul_imm(b, part_c, 0x0100))); in build_dither_mask()
|
| /dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/intel/compiler/ |
| H A D | brw_nir_lower_alpha_to_coverage.c | 75 return nir_ior(b, nir_imul_imm(b, part_a, 0x1111), in build_dither_mask()
76 nir_ior(b, nir_imul_imm(b, part_b, 0x0808), in build_dither_mask()
77 nir_imul_imm(b, part_c, 0x0100))); in build_dither_mask()
|
| /dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/intel/compiler/ |
| H A D | brw_nir_lower_alpha_to_coverage.c | 75 return nir_ior(b, nir_imul_imm(b, part_a, 0x1111), in build_dither_mask()
76 nir_ior(b, nir_imul_imm(b, part_b, 0x0808), in build_dither_mask()
77 nir_imul_imm(b, part_c, 0x0100))); in build_dither_mask()
|
| /dports/graphics/mesa-dri/mesa-21.3.6/src/intel/compiler/ |
| H A D | brw_nir_lower_alpha_to_coverage.c | 75 return nir_ior(b, nir_imul_imm(b, part_a, 0x1111), in build_dither_mask()
76 nir_ior(b, nir_imul_imm(b, part_b, 0x0808), in build_dither_mask()
77 nir_imul_imm(b, part_c, 0x0100))); in build_dither_mask()
|
| /dports/graphics/mesa-dri-classic/mesa-20.2.3/src/intel/compiler/ |
| H A D | brw_nir_lower_alpha_to_coverage.c | 79 nir_imul_imm(b, part_a, 0x1111), in build_dither_mask()
81 nir_imul_imm(b, part_b, 0x0808), in build_dither_mask()
82 nir_imul_imm(b, part_c, 0x0100))); in build_dither_mask()
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| /dports/lang/clover/mesa-21.3.6/src/compiler/nir/tests/ |
| H A D | load_store_vectorizer_tests.cpp | 606 nir_ssa_def *index_base = nir_imul_imm(b, inv, 0xfffffffc); in TEST_F()
1836 nir_ssa_def *first = nir_imul_imm(b, index_base, 0x100000000); in TEST_F()
1879 offset = nir_imul_imm(b, offset, 8); in TEST_F()
1894 offset = nir_imul_imm(b, offset, 12); in TEST_F()
1924 offset = nir_imul_imm(b, offset, 16); in TEST_F()
1945 index = nir_imul_imm(b, index, 3); in TEST_F()
1961 offset = nir_imul_imm(b, offset, 16); in TEST_F()
1975 offset = nir_imul_imm(b, offset, 16); in TEST_F()
1989 offset = nir_imul_imm(b, offset, 16); in TEST_F()
2003 offset = nir_imul_imm(b, offset, 24); in TEST_F()
[all …]
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| /dports/graphics/libosmesa-gallium/mesa-21.3.6/src/compiler/nir/tests/ |
| H A D | load_store_vectorizer_tests.cpp | 606 nir_ssa_def *index_base = nir_imul_imm(b, inv, 0xfffffffc); in TEST_F()
1836 nir_ssa_def *first = nir_imul_imm(b, index_base, 0x100000000); in TEST_F()
1879 offset = nir_imul_imm(b, offset, 8); in TEST_F()
1894 offset = nir_imul_imm(b, offset, 12); in TEST_F()
1924 offset = nir_imul_imm(b, offset, 16); in TEST_F()
1945 index = nir_imul_imm(b, index, 3); in TEST_F()
1961 offset = nir_imul_imm(b, offset, 16); in TEST_F()
1975 offset = nir_imul_imm(b, offset, 16); in TEST_F()
1989 offset = nir_imul_imm(b, offset, 16); in TEST_F()
2003 offset = nir_imul_imm(b, offset, 24); in TEST_F()
[all …]
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| /dports/graphics/mesa-libs/mesa-21.3.6/src/compiler/nir/tests/ |
| H A D | load_store_vectorizer_tests.cpp | 606 nir_ssa_def *index_base = nir_imul_imm(b, inv, 0xfffffffc); in TEST_F()
1836 nir_ssa_def *first = nir_imul_imm(b, index_base, 0x100000000); in TEST_F()
1879 offset = nir_imul_imm(b, offset, 8); in TEST_F()
1894 offset = nir_imul_imm(b, offset, 12); in TEST_F()
1924 offset = nir_imul_imm(b, offset, 16); in TEST_F()
1945 index = nir_imul_imm(b, index, 3); in TEST_F()
1961 offset = nir_imul_imm(b, offset, 16); in TEST_F()
1975 offset = nir_imul_imm(b, offset, 16); in TEST_F()
1989 offset = nir_imul_imm(b, offset, 16); in TEST_F()
2003 offset = nir_imul_imm(b, offset, 24); in TEST_F()
[all …]
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| /dports/graphics/mesa-gallium-va/mesa-21.3.6/src/compiler/nir/tests/ |
| H A D | load_store_vectorizer_tests.cpp | 606 nir_ssa_def *index_base = nir_imul_imm(b, inv, 0xfffffffc); in TEST_F()
1836 nir_ssa_def *first = nir_imul_imm(b, index_base, 0x100000000); in TEST_F()
1879 offset = nir_imul_imm(b, offset, 8); in TEST_F()
1894 offset = nir_imul_imm(b, offset, 12); in TEST_F()
1924 offset = nir_imul_imm(b, offset, 16); in TEST_F()
1945 index = nir_imul_imm(b, index, 3); in TEST_F()
1961 offset = nir_imul_imm(b, offset, 16); in TEST_F()
1975 offset = nir_imul_imm(b, offset, 16); in TEST_F()
1989 offset = nir_imul_imm(b, offset, 16); in TEST_F()
2003 offset = nir_imul_imm(b, offset, 24); in TEST_F()
[all …]
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