| /dports/sysutils/u-boot-tools/u-boot-2020.07/drivers/pinctrl/intel/ |
| H A D | pinctrl.c | 294 offset *= GPIO_DW_SIZE(priv->num_cfgs); in pad_config_offset()
361 for (i = 0; i < priv->num_cfgs; i++) { in pinctrl_configure_pad()
405 GPIO_DW_SIZE(priv->num_cfgs); in intel_pinctrl_get_config_reg_addr()
521 ptr += 1 + priv->num_cfgs, i++) { in pinctrl_config_pads()
561 *pad_countp = size / (1 + priv->num_cfgs); in pinctrl_read_pads()
577 for (val = j = 0; j < priv->num_cfgs + 1; j++) in pinctrl_count_pads()
582 i += priv->num_cfgs + 1; in pinctrl_count_pads()
609 int num_cfgs) in intel_pinctrl_ofdata_to_platdata() argument
623 priv->num_cfgs = num_cfgs; in intel_pinctrl_ofdata_to_platdata()
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| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/pinctrl/intel/ |
| H A D | pinctrl.c | 296 offset *= GPIO_DW_SIZE(priv->num_cfgs); in pad_config_offset()
364 for (i = 0; i < priv->num_cfgs; i++) { in pinctrl_configure_pad()
408 GPIO_DW_SIZE(priv->num_cfgs); in intel_pinctrl_get_config_reg_offset()
533 ptr += 1 + priv->num_cfgs, i++) { in pinctrl_config_pads()
573 *pad_countp = size / (1 + priv->num_cfgs); in pinctrl_read_pads()
589 for (val = j = 0; j < priv->num_cfgs + 1; j++) in pinctrl_count_pads()
594 i += priv->num_cfgs + 1; in pinctrl_count_pads()
620 const struct pad_community *comm, int num_cfgs) in intel_pinctrl_of_to_plat() argument
632 priv->num_cfgs = num_cfgs; in intel_pinctrl_of_to_plat()
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/pinctrl/intel/ |
| H A D | pinctrl.c | 296 offset *= GPIO_DW_SIZE(priv->num_cfgs); in pad_config_offset()
364 for (i = 0; i < priv->num_cfgs; i++) { in pinctrl_configure_pad()
408 GPIO_DW_SIZE(priv->num_cfgs); in intel_pinctrl_get_config_reg_offset()
533 ptr += 1 + priv->num_cfgs, i++) { in pinctrl_config_pads()
573 *pad_countp = size / (1 + priv->num_cfgs); in pinctrl_read_pads()
589 for (val = j = 0; j < priv->num_cfgs + 1; j++) in pinctrl_count_pads()
594 i += priv->num_cfgs + 1; in pinctrl_count_pads()
620 const struct pad_community *comm, int num_cfgs) in intel_pinctrl_of_to_plat() argument
632 priv->num_cfgs = num_cfgs; in intel_pinctrl_of_to_plat()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/pinctrl/intel/ |
| H A D | pinctrl.c | 296 offset *= GPIO_DW_SIZE(priv->num_cfgs); in pad_config_offset()
364 for (i = 0; i < priv->num_cfgs; i++) { in pinctrl_configure_pad()
408 GPIO_DW_SIZE(priv->num_cfgs); in intel_pinctrl_get_config_reg_offset()
533 ptr += 1 + priv->num_cfgs, i++) { in pinctrl_config_pads()
573 *pad_countp = size / (1 + priv->num_cfgs); in pinctrl_read_pads()
589 for (val = j = 0; j < priv->num_cfgs + 1; j++) in pinctrl_count_pads()
594 i += priv->num_cfgs + 1; in pinctrl_count_pads()
620 const struct pad_community *comm, int num_cfgs) in intel_pinctrl_of_to_plat() argument
632 priv->num_cfgs = num_cfgs; in intel_pinctrl_of_to_plat()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/pinctrl/intel/ |
| H A D | pinctrl.c | 296 offset *= GPIO_DW_SIZE(priv->num_cfgs); in pad_config_offset()
364 for (i = 0; i < priv->num_cfgs; i++) { in pinctrl_configure_pad()
408 GPIO_DW_SIZE(priv->num_cfgs); in intel_pinctrl_get_config_reg_offset()
533 ptr += 1 + priv->num_cfgs, i++) { in pinctrl_config_pads()
573 *pad_countp = size / (1 + priv->num_cfgs); in pinctrl_read_pads()
589 for (val = j = 0; j < priv->num_cfgs + 1; j++) in pinctrl_count_pads()
594 i += priv->num_cfgs + 1; in pinctrl_count_pads()
620 const struct pad_community *comm, int num_cfgs) in intel_pinctrl_of_to_plat() argument
632 priv->num_cfgs = num_cfgs; in intel_pinctrl_of_to_plat()
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/pinctrl/intel/ |
| H A D | pinctrl.c | 296 offset *= GPIO_DW_SIZE(priv->num_cfgs); in pad_config_offset()
364 for (i = 0; i < priv->num_cfgs; i++) { in pinctrl_configure_pad()
408 GPIO_DW_SIZE(priv->num_cfgs); in intel_pinctrl_get_config_reg_offset()
533 ptr += 1 + priv->num_cfgs, i++) { in pinctrl_config_pads()
573 *pad_countp = size / (1 + priv->num_cfgs); in pinctrl_read_pads()
589 for (val = j = 0; j < priv->num_cfgs + 1; j++) in pinctrl_count_pads()
594 i += priv->num_cfgs + 1; in pinctrl_count_pads()
620 const struct pad_community *comm, int num_cfgs) in intel_pinctrl_of_to_plat() argument
632 priv->num_cfgs = num_cfgs; in intel_pinctrl_of_to_plat()
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/pinctrl/intel/ |
| H A D | pinctrl.c | 296 offset *= GPIO_DW_SIZE(priv->num_cfgs); in pad_config_offset()
364 for (i = 0; i < priv->num_cfgs; i++) { in pinctrl_configure_pad()
408 GPIO_DW_SIZE(priv->num_cfgs); in intel_pinctrl_get_config_reg_offset()
533 ptr += 1 + priv->num_cfgs, i++) { in pinctrl_config_pads()
573 *pad_countp = size / (1 + priv->num_cfgs); in pinctrl_read_pads()
589 for (val = j = 0; j < priv->num_cfgs + 1; j++) in pinctrl_count_pads()
594 i += priv->num_cfgs + 1; in pinctrl_count_pads()
620 const struct pad_community *comm, int num_cfgs) in intel_pinctrl_of_to_plat() argument
632 priv->num_cfgs = num_cfgs; in intel_pinctrl_of_to_plat()
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/pinctrl/intel/ |
| H A D | pinctrl.c | 296 offset *= GPIO_DW_SIZE(priv->num_cfgs); in pad_config_offset()
364 for (i = 0; i < priv->num_cfgs; i++) { in pinctrl_configure_pad()
408 GPIO_DW_SIZE(priv->num_cfgs); in intel_pinctrl_get_config_reg_offset()
533 ptr += 1 + priv->num_cfgs, i++) { in pinctrl_config_pads()
573 *pad_countp = size / (1 + priv->num_cfgs); in pinctrl_read_pads()
589 for (val = j = 0; j < priv->num_cfgs + 1; j++) in pinctrl_count_pads()
594 i += priv->num_cfgs + 1; in pinctrl_count_pads()
620 const struct pad_community *comm, int num_cfgs) in intel_pinctrl_of_to_plat() argument
632 priv->num_cfgs = num_cfgs; in intel_pinctrl_of_to_plat()
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| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/pinctrl/intel/ |
| H A D | pinctrl.c | 296 offset *= GPIO_DW_SIZE(priv->num_cfgs); in pad_config_offset()
364 for (i = 0; i < priv->num_cfgs; i++) { in pinctrl_configure_pad()
408 GPIO_DW_SIZE(priv->num_cfgs); in intel_pinctrl_get_config_reg_offset()
533 ptr += 1 + priv->num_cfgs, i++) { in pinctrl_config_pads()
573 *pad_countp = size / (1 + priv->num_cfgs); in pinctrl_read_pads()
589 for (val = j = 0; j < priv->num_cfgs + 1; j++) in pinctrl_count_pads()
594 i += priv->num_cfgs + 1; in pinctrl_count_pads()
620 const struct pad_community *comm, int num_cfgs) in intel_pinctrl_of_to_plat() argument
632 priv->num_cfgs = num_cfgs; in intel_pinctrl_of_to_plat()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/pinctrl/intel/ |
| H A D | pinctrl.c | 296 offset *= GPIO_DW_SIZE(priv->num_cfgs); in pad_config_offset()
364 for (i = 0; i < priv->num_cfgs; i++) { in pinctrl_configure_pad()
408 GPIO_DW_SIZE(priv->num_cfgs); in intel_pinctrl_get_config_reg_offset()
533 ptr += 1 + priv->num_cfgs, i++) { in pinctrl_config_pads()
573 *pad_countp = size / (1 + priv->num_cfgs); in pinctrl_read_pads()
589 for (val = j = 0; j < priv->num_cfgs + 1; j++) in pinctrl_count_pads()
594 i += priv->num_cfgs + 1; in pinctrl_count_pads()
620 const struct pad_community *comm, int num_cfgs) in intel_pinctrl_of_to_plat() argument
632 priv->num_cfgs = num_cfgs; in intel_pinctrl_of_to_plat()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/pinctrl/intel/ |
| H A D | pinctrl.c | 296 offset *= GPIO_DW_SIZE(priv->num_cfgs); in pad_config_offset()
364 for (i = 0; i < priv->num_cfgs; i++) { in pinctrl_configure_pad()
408 GPIO_DW_SIZE(priv->num_cfgs); in intel_pinctrl_get_config_reg_offset()
533 ptr += 1 + priv->num_cfgs, i++) { in pinctrl_config_pads()
573 *pad_countp = size / (1 + priv->num_cfgs); in pinctrl_read_pads()
589 for (val = j = 0; j < priv->num_cfgs + 1; j++) in pinctrl_count_pads()
594 i += priv->num_cfgs + 1; in pinctrl_count_pads()
620 const struct pad_community *comm, int num_cfgs) in intel_pinctrl_of_to_plat() argument
632 priv->num_cfgs = num_cfgs; in intel_pinctrl_of_to_plat()
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| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/pinctrl/intel/ |
| H A D | pinctrl.c | 296 offset *= GPIO_DW_SIZE(priv->num_cfgs); in pad_config_offset()
364 for (i = 0; i < priv->num_cfgs; i++) { in pinctrl_configure_pad()
408 GPIO_DW_SIZE(priv->num_cfgs); in intel_pinctrl_get_config_reg_offset()
533 ptr += 1 + priv->num_cfgs, i++) { in pinctrl_config_pads()
573 *pad_countp = size / (1 + priv->num_cfgs); in pinctrl_read_pads()
589 for (val = j = 0; j < priv->num_cfgs + 1; j++) in pinctrl_count_pads()
594 i += priv->num_cfgs + 1; in pinctrl_count_pads()
620 const struct pad_community *comm, int num_cfgs) in intel_pinctrl_of_to_plat() argument
632 priv->num_cfgs = num_cfgs; in intel_pinctrl_of_to_plat()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/pinctrl/intel/ |
| H A D | pinctrl.c | 296 offset *= GPIO_DW_SIZE(priv->num_cfgs); in pad_config_offset()
364 for (i = 0; i < priv->num_cfgs; i++) { in pinctrl_configure_pad()
408 GPIO_DW_SIZE(priv->num_cfgs); in intel_pinctrl_get_config_reg_offset()
533 ptr += 1 + priv->num_cfgs, i++) { in pinctrl_config_pads()
573 *pad_countp = size / (1 + priv->num_cfgs); in pinctrl_read_pads()
589 for (val = j = 0; j < priv->num_cfgs + 1; j++) in pinctrl_count_pads()
594 i += priv->num_cfgs + 1; in pinctrl_count_pads()
620 const struct pad_community *comm, int num_cfgs) in intel_pinctrl_of_to_plat() argument
632 priv->num_cfgs = num_cfgs; in intel_pinctrl_of_to_plat()
|
| /dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/drivers/pinctrl/intel/ |
| H A D | pinctrl.c | 296 offset *= GPIO_DW_SIZE(priv->num_cfgs); in pad_config_offset()
364 for (i = 0; i < priv->num_cfgs; i++) { in pinctrl_configure_pad()
408 GPIO_DW_SIZE(priv->num_cfgs); in intel_pinctrl_get_config_reg_offset()
533 ptr += 1 + priv->num_cfgs, i++) { in pinctrl_config_pads()
573 *pad_countp = size / (1 + priv->num_cfgs); in pinctrl_read_pads()
589 for (val = j = 0; j < priv->num_cfgs + 1; j++) in pinctrl_count_pads()
594 i += priv->num_cfgs + 1; in pinctrl_count_pads()
620 const struct pad_community *comm, int num_cfgs) in intel_pinctrl_of_to_plat() argument
632 priv->num_cfgs = num_cfgs; in intel_pinctrl_of_to_plat()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/pinctrl/intel/ |
| H A D | pinctrl.c | 296 offset *= GPIO_DW_SIZE(priv->num_cfgs); in pad_config_offset()
364 for (i = 0; i < priv->num_cfgs; i++) { in pinctrl_configure_pad()
408 GPIO_DW_SIZE(priv->num_cfgs); in intel_pinctrl_get_config_reg_offset()
533 ptr += 1 + priv->num_cfgs, i++) { in pinctrl_config_pads()
573 *pad_countp = size / (1 + priv->num_cfgs); in pinctrl_read_pads()
589 for (val = j = 0; j < priv->num_cfgs + 1; j++) in pinctrl_count_pads()
594 i += priv->num_cfgs + 1; in pinctrl_count_pads()
620 const struct pad_community *comm, int num_cfgs) in intel_pinctrl_of_to_plat() argument
632 priv->num_cfgs = num_cfgs; in intel_pinctrl_of_to_plat()
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| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/pinctrl/intel/ |
| H A D | pinctrl.c | 296 offset *= GPIO_DW_SIZE(priv->num_cfgs); in pad_config_offset()
364 for (i = 0; i < priv->num_cfgs; i++) { in pinctrl_configure_pad()
408 GPIO_DW_SIZE(priv->num_cfgs); in intel_pinctrl_get_config_reg_offset()
533 ptr += 1 + priv->num_cfgs, i++) { in pinctrl_config_pads()
573 *pad_countp = size / (1 + priv->num_cfgs); in pinctrl_read_pads()
589 for (val = j = 0; j < priv->num_cfgs + 1; j++) in pinctrl_count_pads()
594 i += priv->num_cfgs + 1; in pinctrl_count_pads()
620 const struct pad_community *comm, int num_cfgs) in intel_pinctrl_of_to_plat() argument
632 priv->num_cfgs = num_cfgs; in intel_pinctrl_of_to_plat()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/pinctrl/intel/ |
| H A D | pinctrl.c | 296 offset *= GPIO_DW_SIZE(priv->num_cfgs); in pad_config_offset()
364 for (i = 0; i < priv->num_cfgs; i++) { in pinctrl_configure_pad()
408 GPIO_DW_SIZE(priv->num_cfgs); in intel_pinctrl_get_config_reg_offset()
533 ptr += 1 + priv->num_cfgs, i++) { in pinctrl_config_pads()
573 *pad_countp = size / (1 + priv->num_cfgs); in pinctrl_read_pads()
589 for (val = j = 0; j < priv->num_cfgs + 1; j++) in pinctrl_count_pads()
594 i += priv->num_cfgs + 1; in pinctrl_count_pads()
620 const struct pad_community *comm, int num_cfgs) in intel_pinctrl_of_to_plat() argument
632 priv->num_cfgs = num_cfgs; in intel_pinctrl_of_to_plat()
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/pinctrl/intel/ |
| H A D | pinctrl.c | 296 offset *= GPIO_DW_SIZE(priv->num_cfgs); in pad_config_offset()
364 for (i = 0; i < priv->num_cfgs; i++) { in pinctrl_configure_pad()
408 GPIO_DW_SIZE(priv->num_cfgs); in intel_pinctrl_get_config_reg_offset()
533 ptr += 1 + priv->num_cfgs, i++) { in pinctrl_config_pads()
573 *pad_countp = size / (1 + priv->num_cfgs); in pinctrl_read_pads()
589 for (val = j = 0; j < priv->num_cfgs + 1; j++) in pinctrl_count_pads()
594 i += priv->num_cfgs + 1; in pinctrl_count_pads()
620 const struct pad_community *comm, int num_cfgs) in intel_pinctrl_of_to_plat() argument
632 priv->num_cfgs = num_cfgs; in intel_pinctrl_of_to_plat()
|
| /dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/pinctrl/intel/ |
| H A D | pinctrl.c | 296 offset *= GPIO_DW_SIZE(priv->num_cfgs); in pad_config_offset()
364 for (i = 0; i < priv->num_cfgs; i++) { in pinctrl_configure_pad()
408 GPIO_DW_SIZE(priv->num_cfgs); in intel_pinctrl_get_config_reg_offset()
533 ptr += 1 + priv->num_cfgs, i++) { in pinctrl_config_pads()
573 *pad_countp = size / (1 + priv->num_cfgs); in pinctrl_read_pads()
589 for (val = j = 0; j < priv->num_cfgs + 1; j++) in pinctrl_count_pads()
594 i += priv->num_cfgs + 1; in pinctrl_count_pads()
620 const struct pad_community *comm, int num_cfgs) in intel_pinctrl_of_to_plat() argument
632 priv->num_cfgs = num_cfgs; in intel_pinctrl_of_to_plat()
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/pinctrl/intel/ |
| H A D | pinctrl.c | 296 offset *= GPIO_DW_SIZE(priv->num_cfgs); in pad_config_offset()
364 for (i = 0; i < priv->num_cfgs; i++) { in pinctrl_configure_pad()
408 GPIO_DW_SIZE(priv->num_cfgs); in intel_pinctrl_get_config_reg_offset()
533 ptr += 1 + priv->num_cfgs, i++) { in pinctrl_config_pads()
573 *pad_countp = size / (1 + priv->num_cfgs); in pinctrl_read_pads()
589 for (val = j = 0; j < priv->num_cfgs + 1; j++) in pinctrl_count_pads()
594 i += priv->num_cfgs + 1; in pinctrl_count_pads()
620 const struct pad_community *comm, int num_cfgs) in intel_pinctrl_of_to_plat() argument
632 priv->num_cfgs = num_cfgs; in intel_pinctrl_of_to_plat()
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| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/pinctrl/intel/ |
| H A D | pinctrl.c | 296 offset *= GPIO_DW_SIZE(priv->num_cfgs); in pad_config_offset()
364 for (i = 0; i < priv->num_cfgs; i++) { in pinctrl_configure_pad()
408 GPIO_DW_SIZE(priv->num_cfgs); in intel_pinctrl_get_config_reg_offset()
533 ptr += 1 + priv->num_cfgs, i++) { in pinctrl_config_pads()
573 *pad_countp = size / (1 + priv->num_cfgs); in pinctrl_read_pads()
589 for (val = j = 0; j < priv->num_cfgs + 1; j++) in pinctrl_count_pads()
594 i += priv->num_cfgs + 1; in pinctrl_count_pads()
620 const struct pad_community *comm, int num_cfgs) in intel_pinctrl_of_to_plat() argument
632 priv->num_cfgs = num_cfgs; in intel_pinctrl_of_to_plat()
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| /dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/drivers/pinctrl/intel/ |
| H A D | pinctrl.c | 296 offset *= GPIO_DW_SIZE(priv->num_cfgs); in pad_config_offset()
364 for (i = 0; i < priv->num_cfgs; i++) { in pinctrl_configure_pad()
408 GPIO_DW_SIZE(priv->num_cfgs); in intel_pinctrl_get_config_reg_offset()
533 ptr += 1 + priv->num_cfgs, i++) { in pinctrl_config_pads()
573 *pad_countp = size / (1 + priv->num_cfgs); in pinctrl_read_pads()
589 for (val = j = 0; j < priv->num_cfgs + 1; j++) in pinctrl_count_pads()
594 i += priv->num_cfgs + 1; in pinctrl_count_pads()
620 const struct pad_community *comm, int num_cfgs) in intel_pinctrl_of_to_plat() argument
632 priv->num_cfgs = num_cfgs; in intel_pinctrl_of_to_plat()
|
| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/drivers/pinctrl/intel/ |
| H A D | pinctrl.c | 296 offset *= GPIO_DW_SIZE(priv->num_cfgs); in pad_config_offset()
364 for (i = 0; i < priv->num_cfgs; i++) { in pinctrl_configure_pad()
408 GPIO_DW_SIZE(priv->num_cfgs); in intel_pinctrl_get_config_reg_offset()
533 ptr += 1 + priv->num_cfgs, i++) { in pinctrl_config_pads()
573 *pad_countp = size / (1 + priv->num_cfgs); in pinctrl_read_pads()
589 for (val = j = 0; j < priv->num_cfgs + 1; j++) in pinctrl_count_pads()
594 i += priv->num_cfgs + 1; in pinctrl_count_pads()
620 const struct pad_community *comm, int num_cfgs) in intel_pinctrl_of_to_plat() argument
632 priv->num_cfgs = num_cfgs; in intel_pinctrl_of_to_plat()
|
| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/pinctrl/intel/ |
| H A D | pinctrl.c | 296 offset *= GPIO_DW_SIZE(priv->num_cfgs); in pad_config_offset()
364 for (i = 0; i < priv->num_cfgs; i++) { in pinctrl_configure_pad()
408 GPIO_DW_SIZE(priv->num_cfgs); in intel_pinctrl_get_config_reg_offset()
533 ptr += 1 + priv->num_cfgs, i++) { in pinctrl_config_pads()
573 *pad_countp = size / (1 + priv->num_cfgs); in pinctrl_read_pads()
589 for (val = j = 0; j < priv->num_cfgs + 1; j++) in pinctrl_count_pads()
594 i += priv->num_cfgs + 1; in pinctrl_count_pads()
620 const struct pad_community *comm, int num_cfgs) in intel_pinctrl_of_to_plat() argument
632 priv->num_cfgs = num_cfgs; in intel_pinctrl_of_to_plat()
|
| /dports/sysutils/u-boot-pine-h64/u-boot-2021.07/drivers/pinctrl/intel/ |
| H A D | pinctrl.c | 296 offset *= GPIO_DW_SIZE(priv->num_cfgs);
364 for (i = 0; i < priv->num_cfgs; i++) {
408 GPIO_DW_SIZE(priv->num_cfgs);
533 ptr += 1 + priv->num_cfgs, i++) {
573 *pad_countp = size / (1 + priv->num_cfgs);
589 for (val = j = 0; j < priv->num_cfgs + 1; j++)
594 i += priv->num_cfgs + 1;
620 const struct pad_community *comm, int num_cfgs)
632 priv->num_cfgs = num_cfgs;
|