| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 141 u32 win_ctrl_reg, num_of_win_regs; in ddr3_restore_and_set_final_windows() local
151 num_of_win_regs = 8; in ddr3_restore_and_set_final_windows()
154 num_of_win_regs = 16; in ddr3_restore_and_set_final_windows()
158 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_restore_and_set_final_windows()
201 u32 num_of_win_regs, win_jump_index; in ddr3_save_and_set_training_windows() local
211 num_of_win_regs = 8; in ddr3_save_and_set_training_windows()
217 num_of_win_regs = 16; in ddr3_save_and_set_training_windows()
225 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_save_and_set_training_windows()
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 141 u32 win_ctrl_reg, num_of_win_regs; in ddr3_restore_and_set_final_windows() local
151 num_of_win_regs = 8; in ddr3_restore_and_set_final_windows()
154 num_of_win_regs = 16; in ddr3_restore_and_set_final_windows()
158 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_restore_and_set_final_windows()
201 u32 num_of_win_regs, win_jump_index; in ddr3_save_and_set_training_windows() local
211 num_of_win_regs = 8; in ddr3_save_and_set_training_windows()
217 num_of_win_regs = 16; in ddr3_save_and_set_training_windows()
225 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_save_and_set_training_windows()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 143 u32 win_ctrl_reg, num_of_win_regs; in ddr3_restore_and_set_final_windows() local
153 num_of_win_regs = 8; in ddr3_restore_and_set_final_windows()
156 num_of_win_regs = 16; in ddr3_restore_and_set_final_windows()
160 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_restore_and_set_final_windows()
203 u32 num_of_win_regs, win_jump_index; in ddr3_save_and_set_training_windows() local
213 num_of_win_regs = 8; in ddr3_save_and_set_training_windows()
219 num_of_win_regs = 16; in ddr3_save_and_set_training_windows()
227 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_save_and_set_training_windows()
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 143 u32 win_ctrl_reg, num_of_win_regs; in ddr3_restore_and_set_final_windows() local
153 num_of_win_regs = 8; in ddr3_restore_and_set_final_windows()
156 num_of_win_regs = 16; in ddr3_restore_and_set_final_windows()
160 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_restore_and_set_final_windows()
203 u32 num_of_win_regs, win_jump_index; in ddr3_save_and_set_training_windows() local
213 num_of_win_regs = 8; in ddr3_save_and_set_training_windows()
219 num_of_win_regs = 16; in ddr3_save_and_set_training_windows()
227 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_save_and_set_training_windows()
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 143 u32 win_ctrl_reg, num_of_win_regs; in ddr3_restore_and_set_final_windows() local
153 num_of_win_regs = 8; in ddr3_restore_and_set_final_windows()
156 num_of_win_regs = 16; in ddr3_restore_and_set_final_windows()
160 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_restore_and_set_final_windows()
203 u32 num_of_win_regs, win_jump_index; in ddr3_save_and_set_training_windows() local
213 num_of_win_regs = 8; in ddr3_save_and_set_training_windows()
219 num_of_win_regs = 16; in ddr3_save_and_set_training_windows()
227 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_save_and_set_training_windows()
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 143 u32 win_ctrl_reg, num_of_win_regs; in ddr3_restore_and_set_final_windows() local
153 num_of_win_regs = 8; in ddr3_restore_and_set_final_windows()
156 num_of_win_regs = 16; in ddr3_restore_and_set_final_windows()
160 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_restore_and_set_final_windows()
203 u32 num_of_win_regs, win_jump_index; in ddr3_save_and_set_training_windows() local
213 num_of_win_regs = 8; in ddr3_save_and_set_training_windows()
219 num_of_win_regs = 16; in ddr3_save_and_set_training_windows()
227 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_save_and_set_training_windows()
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 141 u32 win_ctrl_reg, num_of_win_regs; in ddr3_restore_and_set_final_windows() local
151 num_of_win_regs = 8; in ddr3_restore_and_set_final_windows()
154 num_of_win_regs = 16; in ddr3_restore_and_set_final_windows()
158 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_restore_and_set_final_windows()
201 u32 num_of_win_regs, win_jump_index; in ddr3_save_and_set_training_windows() local
211 num_of_win_regs = 8; in ddr3_save_and_set_training_windows()
217 num_of_win_regs = 16; in ddr3_save_and_set_training_windows()
225 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_save_and_set_training_windows()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 143 u32 win_ctrl_reg, num_of_win_regs; in ddr3_restore_and_set_final_windows() local
153 num_of_win_regs = 8; in ddr3_restore_and_set_final_windows()
156 num_of_win_regs = 16; in ddr3_restore_and_set_final_windows()
160 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_restore_and_set_final_windows()
203 u32 num_of_win_regs, win_jump_index; in ddr3_save_and_set_training_windows() local
213 num_of_win_regs = 8; in ddr3_save_and_set_training_windows()
219 num_of_win_regs = 16; in ddr3_save_and_set_training_windows()
227 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_save_and_set_training_windows()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 143 u32 win_ctrl_reg, num_of_win_regs; in ddr3_restore_and_set_final_windows() local
153 num_of_win_regs = 8; in ddr3_restore_and_set_final_windows()
156 num_of_win_regs = 16; in ddr3_restore_and_set_final_windows()
160 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_restore_and_set_final_windows()
203 u32 num_of_win_regs, win_jump_index; in ddr3_save_and_set_training_windows() local
213 num_of_win_regs = 8; in ddr3_save_and_set_training_windows()
219 num_of_win_regs = 16; in ddr3_save_and_set_training_windows()
227 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_save_and_set_training_windows()
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 143 u32 win_ctrl_reg, num_of_win_regs; in ddr3_restore_and_set_final_windows() local
153 num_of_win_regs = 8; in ddr3_restore_and_set_final_windows()
156 num_of_win_regs = 16; in ddr3_restore_and_set_final_windows()
160 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_restore_and_set_final_windows()
203 u32 num_of_win_regs, win_jump_index; in ddr3_save_and_set_training_windows() local
213 num_of_win_regs = 8; in ddr3_save_and_set_training_windows()
219 num_of_win_regs = 16; in ddr3_save_and_set_training_windows()
227 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_save_and_set_training_windows()
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 143 u32 win_ctrl_reg, num_of_win_regs; in ddr3_restore_and_set_final_windows() local
153 num_of_win_regs = 8; in ddr3_restore_and_set_final_windows()
156 num_of_win_regs = 16; in ddr3_restore_and_set_final_windows()
160 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_restore_and_set_final_windows()
203 u32 num_of_win_regs, win_jump_index; in ddr3_save_and_set_training_windows() local
213 num_of_win_regs = 8; in ddr3_save_and_set_training_windows()
219 num_of_win_regs = 16; in ddr3_save_and_set_training_windows()
227 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_save_and_set_training_windows()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 143 u32 win_ctrl_reg, num_of_win_regs; in ddr3_restore_and_set_final_windows() local
153 num_of_win_regs = 8; in ddr3_restore_and_set_final_windows()
156 num_of_win_regs = 16; in ddr3_restore_and_set_final_windows()
160 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_restore_and_set_final_windows()
203 u32 num_of_win_regs, win_jump_index; in ddr3_save_and_set_training_windows() local
213 num_of_win_regs = 8; in ddr3_save_and_set_training_windows()
219 num_of_win_regs = 16; in ddr3_save_and_set_training_windows()
227 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_save_and_set_training_windows()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 143 u32 win_ctrl_reg, num_of_win_regs; in ddr3_restore_and_set_final_windows() local
153 num_of_win_regs = 8; in ddr3_restore_and_set_final_windows()
156 num_of_win_regs = 16; in ddr3_restore_and_set_final_windows()
160 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_restore_and_set_final_windows()
203 u32 num_of_win_regs, win_jump_index; in ddr3_save_and_set_training_windows() local
213 num_of_win_regs = 8; in ddr3_save_and_set_training_windows()
219 num_of_win_regs = 16; in ddr3_save_and_set_training_windows()
227 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_save_and_set_training_windows()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 143 u32 win_ctrl_reg, num_of_win_regs; in ddr3_restore_and_set_final_windows() local
153 num_of_win_regs = 8; in ddr3_restore_and_set_final_windows()
156 num_of_win_regs = 16; in ddr3_restore_and_set_final_windows()
160 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_restore_and_set_final_windows()
203 u32 num_of_win_regs, win_jump_index; in ddr3_save_and_set_training_windows() local
213 num_of_win_regs = 8; in ddr3_save_and_set_training_windows()
219 num_of_win_regs = 16; in ddr3_save_and_set_training_windows()
227 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_save_and_set_training_windows()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 143 u32 win_ctrl_reg, num_of_win_regs; in ddr3_restore_and_set_final_windows() local
153 num_of_win_regs = 8; in ddr3_restore_and_set_final_windows()
156 num_of_win_regs = 16; in ddr3_restore_and_set_final_windows()
160 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_restore_and_set_final_windows()
203 u32 num_of_win_regs, win_jump_index; in ddr3_save_and_set_training_windows() local
213 num_of_win_regs = 8; in ddr3_save_and_set_training_windows()
219 num_of_win_regs = 16; in ddr3_save_and_set_training_windows()
227 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_save_and_set_training_windows()
|
| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 143 u32 win_ctrl_reg, num_of_win_regs; in ddr3_restore_and_set_final_windows() local
153 num_of_win_regs = 8; in ddr3_restore_and_set_final_windows()
156 num_of_win_regs = 16; in ddr3_restore_and_set_final_windows()
160 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_restore_and_set_final_windows()
203 u32 num_of_win_regs, win_jump_index; in ddr3_save_and_set_training_windows() local
213 num_of_win_regs = 8; in ddr3_save_and_set_training_windows()
219 num_of_win_regs = 16; in ddr3_save_and_set_training_windows()
227 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_save_and_set_training_windows()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 143 u32 win_ctrl_reg, num_of_win_regs; in ddr3_restore_and_set_final_windows() local
153 num_of_win_regs = 8; in ddr3_restore_and_set_final_windows()
156 num_of_win_regs = 16; in ddr3_restore_and_set_final_windows()
160 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_restore_and_set_final_windows()
203 u32 num_of_win_regs, win_jump_index; in ddr3_save_and_set_training_windows() local
213 num_of_win_regs = 8; in ddr3_save_and_set_training_windows()
219 num_of_win_regs = 16; in ddr3_save_and_set_training_windows()
227 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_save_and_set_training_windows()
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 143 u32 win_ctrl_reg, num_of_win_regs; in ddr3_restore_and_set_final_windows() local
153 num_of_win_regs = 8; in ddr3_restore_and_set_final_windows()
156 num_of_win_regs = 16; in ddr3_restore_and_set_final_windows()
160 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_restore_and_set_final_windows()
203 u32 num_of_win_regs, win_jump_index; in ddr3_save_and_set_training_windows() local
213 num_of_win_regs = 8; in ddr3_save_and_set_training_windows()
219 num_of_win_regs = 16; in ddr3_save_and_set_training_windows()
227 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_save_and_set_training_windows()
|
| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 143 u32 win_ctrl_reg, num_of_win_regs; in ddr3_restore_and_set_final_windows() local
153 num_of_win_regs = 8; in ddr3_restore_and_set_final_windows()
156 num_of_win_regs = 16; in ddr3_restore_and_set_final_windows()
160 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_restore_and_set_final_windows()
203 u32 num_of_win_regs, win_jump_index; in ddr3_save_and_set_training_windows() local
213 num_of_win_regs = 8; in ddr3_save_and_set_training_windows()
219 num_of_win_regs = 16; in ddr3_save_and_set_training_windows()
227 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_save_and_set_training_windows()
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 143 u32 win_ctrl_reg, num_of_win_regs; in ddr3_restore_and_set_final_windows() local
153 num_of_win_regs = 8; in ddr3_restore_and_set_final_windows()
156 num_of_win_regs = 16; in ddr3_restore_and_set_final_windows()
160 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_restore_and_set_final_windows()
203 u32 num_of_win_regs, win_jump_index; in ddr3_save_and_set_training_windows() local
213 num_of_win_regs = 8; in ddr3_save_and_set_training_windows()
219 num_of_win_regs = 16; in ddr3_save_and_set_training_windows()
227 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_save_and_set_training_windows()
|
| /dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 143 u32 win_ctrl_reg, num_of_win_regs; in ddr3_restore_and_set_final_windows() local
153 num_of_win_regs = 8; in ddr3_restore_and_set_final_windows()
156 num_of_win_regs = 16; in ddr3_restore_and_set_final_windows()
160 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_restore_and_set_final_windows()
203 u32 num_of_win_regs, win_jump_index; in ddr3_save_and_set_training_windows() local
213 num_of_win_regs = 8; in ddr3_save_and_set_training_windows()
219 num_of_win_regs = 16; in ddr3_save_and_set_training_windows()
227 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_save_and_set_training_windows()
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 141 u32 win_ctrl_reg, num_of_win_regs; in ddr3_restore_and_set_final_windows() local
151 num_of_win_regs = 8; in ddr3_restore_and_set_final_windows()
154 num_of_win_regs = 16; in ddr3_restore_and_set_final_windows()
158 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_restore_and_set_final_windows()
201 u32 num_of_win_regs, win_jump_index; in ddr3_save_and_set_training_windows() local
211 num_of_win_regs = 8; in ddr3_save_and_set_training_windows()
217 num_of_win_regs = 16; in ddr3_save_and_set_training_windows()
225 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_save_and_set_training_windows()
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 143 u32 win_ctrl_reg, num_of_win_regs; in ddr3_restore_and_set_final_windows() local
153 num_of_win_regs = 8; in ddr3_restore_and_set_final_windows()
156 num_of_win_regs = 16; in ddr3_restore_and_set_final_windows()
160 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_restore_and_set_final_windows()
203 u32 num_of_win_regs, win_jump_index; in ddr3_save_and_set_training_windows() local
213 num_of_win_regs = 8; in ddr3_save_and_set_training_windows()
219 num_of_win_regs = 16; in ddr3_save_and_set_training_windows()
227 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_save_and_set_training_windows()
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 143 u32 win_ctrl_reg, num_of_win_regs; in ddr3_restore_and_set_final_windows() local
153 num_of_win_regs = 8; in ddr3_restore_and_set_final_windows()
156 num_of_win_regs = 16; in ddr3_restore_and_set_final_windows()
160 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_restore_and_set_final_windows()
203 u32 num_of_win_regs, win_jump_index; in ddr3_save_and_set_training_windows() local
213 num_of_win_regs = 8; in ddr3_save_and_set_training_windows()
219 num_of_win_regs = 16; in ddr3_save_and_set_training_windows()
227 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_save_and_set_training_windows()
|
| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.c | 143 u32 win_ctrl_reg, num_of_win_regs; in ddr3_restore_and_set_final_windows() local
153 num_of_win_regs = 8; in ddr3_restore_and_set_final_windows()
156 num_of_win_regs = 16; in ddr3_restore_and_set_final_windows()
160 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_restore_and_set_final_windows()
203 u32 num_of_win_regs, win_jump_index; in ddr3_save_and_set_training_windows() local
213 num_of_win_regs = 8; in ddr3_save_and_set_training_windows()
219 num_of_win_regs = 16; in ddr3_save_and_set_training_windows()
227 for (ui = 0; ui < num_of_win_regs; ui++) in ddr3_save_and_set_training_windows()
|