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Searched refs:odn_mclk_table (Results 1 – 3 of 3) sorted by relevance

/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu7_hwmgr.c4182 struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels); in smu7_populate_and_upload_sclk_mclk_dpm_levels() local
4196 dpm_table->mclk_table.dpm_levels[count].enabled = odn_mclk_table->entries[count].enabled; in smu7_populate_and_upload_sclk_mclk_dpm_levels()
4197 dpm_table->mclk_table.dpm_levels[count].value = odn_mclk_table->entries[count].clock; in smu7_populate_and_upload_sclk_mclk_dpm_levels()
4898 struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels); in smu7_print_clock_levels() local
4961 for (i = 0; i < odn_mclk_table->num_of_pl; i++) in smu7_print_clock_levels()
4963 i, odn_mclk_table->entries[i].clock/100, in smu7_print_clock_levels()
4964 odn_mclk_table->entries[i].vddc); in smu7_print_clock_levels()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu7_hwmgr.c4182 struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels); in smu7_populate_and_upload_sclk_mclk_dpm_levels() local
4196 dpm_table->mclk_table.dpm_levels[count].enabled = odn_mclk_table->entries[count].enabled; in smu7_populate_and_upload_sclk_mclk_dpm_levels()
4197 dpm_table->mclk_table.dpm_levels[count].value = odn_mclk_table->entries[count].clock; in smu7_populate_and_upload_sclk_mclk_dpm_levels()
4898 struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels); in smu7_print_clock_levels() local
4961 for (i = 0; i < odn_mclk_table->num_of_pl; i++) in smu7_print_clock_levels()
4963 i, odn_mclk_table->entries[i].clock/100, in smu7_print_clock_levels()
4964 odn_mclk_table->entries[i].vddc); in smu7_print_clock_levels()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu7_hwmgr.c4182 struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels); in smu7_populate_and_upload_sclk_mclk_dpm_levels() local
4196 dpm_table->mclk_table.dpm_levels[count].enabled = odn_mclk_table->entries[count].enabled; in smu7_populate_and_upload_sclk_mclk_dpm_levels()
4197 dpm_table->mclk_table.dpm_levels[count].value = odn_mclk_table->entries[count].clock; in smu7_populate_and_upload_sclk_mclk_dpm_levels()
4898 struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels); in smu7_print_clock_levels() local
4961 for (i = 0; i < odn_mclk_table->num_of_pl; i++) in smu7_print_clock_levels()
4963 i, odn_mclk_table->entries[i].clock/100, in smu7_print_clock_levels()
4964 odn_mclk_table->entries[i].vddc); in smu7_print_clock_levels()