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Searched refs:op1s (Results 1 – 25 of 29) sorted by relevance

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/dports/graphics/opencv/opencv-4.5.3/modules/video/src/
H A Dvariational_refinement.cpp126 vector<void *> op1s; member
504 vector<void *> op1s; in prepareBuffers() local
505 op1s.push_back((void *)&I0); in prepareBuffers()
506 op1s.push_back((void *)&warpedI); in prepareBuffers()
522 vector<void *> op1s; in prepareBuffers() local
525 op1s.push_back((void *)&Iz); in prepareBuffers()
526 op1s.push_back((void *)&Iz); in prepareBuffers()
547 vector<void *> op1s; in prepareBuffers() local
548 op1s.push_back((void *)&Ix); in prepareBuffers()
549 op1s.push_back((void *)&Ix); in prepareBuffers()
[all …]
/dports/emulators/dps8m/dps8m-572f79bb4f0f84a8b16c3892c894c2b9ed64b458/src/dps8/
H A Ddps8_utils.c1128 int128 op1s = SIGNEXT72_128 (and_128 (op1, MASK72)); in cmp72() local
1130 sim_debug (DBG_TRACEEXT, & cpu_dev, "op1s %016"PRIx64"%016"PRIx64"\n", op1s.h, op1s.l); in cmp72()
1135 int128 op1s = SIGNEXT72_128 (op1 & MASK72); in cmp72() local
1137 …BG_TRACEEXT, & cpu_dev, "op1s %016"PRIx64"%016"PRIx64"\n", (uint64_t) (op1s>>64), (uint64_t) op1s); in cmp72()
1141 if (isgt_s128 (op1s, op2s)) in cmp72()
1143 if (op1s > op2s) in cmp72()
1160 else if (iseq_128 (cast_128 (op1s), cast_128 (op2s))) in cmp72()
1162 else if (op1s == op2s) in cmp72()
/dports/databases/mongodb36/mongodb-src-r3.6.23/src/third_party/wiredtiger/test/suite/
H A Dtest_txn04.py57 op1s = [ variable in test_txn04
65 scenarios = make_scenarios(types, op1s, txn1s)
H A Dtest_txn09.py51 op1s = [ variable in test_txn09
80 op1s, txn1s, op2s, txn2s, op3s, txn3s, op4s, txn4s,
H A Dtest_txn05.py58 op1s = [ variable in test_txn05
66 scenarios = make_scenarios(types, op1s, txn1s)
H A Dtest_txn07.py59 op1s = [ variable in test_txn07
73 scenarios = make_scenarios(types, op1s, txn1s, compress,
H A Dtest_txn02.py59 op1s = [ variable in test_txn02
88 op1s, txn1s, op2s, txn2s, op3s, txn3s, op4s, txn4s,
/dports/www/qt5-webengine/qtwebengine-everywhere-src-5.15.2/src/3rdparty/chromium/sandbox/win/src/
H A Dpolicy_opcodes_unittest.cc340 PolicyOpcode* op1s = opcode_maker.MakeOpWStringMatch( in TEST() local
342 ASSERT_NE(nullptr, op1s); in TEST()
346 EXPECT_EQ(EVAL_FALSE, op1s->Evaluate(&pp_tc1, 1, &mc1)); in TEST()
/dports/www/firefox-esr/firefox-91.8.0/security/sandbox/chromium/sandbox/win/src/
H A Dpolicy_opcodes_unittest.cc340 PolicyOpcode* op1s = opcode_maker.MakeOpWStringMatch(
342 ASSERT_NE(nullptr, op1s);
346 EXPECT_EQ(EVAL_FALSE, op1s->Evaluate(&pp_tc1, 1, &mc1));
/dports/www/firefox/firefox-99.0/security/sandbox/chromium/sandbox/win/src/
H A Dpolicy_opcodes_unittest.cc340 PolicyOpcode* op1s = opcode_maker.MakeOpWStringMatch( in TEST() local
342 ASSERT_NE(nullptr, op1s); in TEST()
346 EXPECT_EQ(EVAL_FALSE, op1s->Evaluate(&pp_tc1, 1, &mc1)); in TEST()
/dports/lang/spidermonkey60/firefox-60.9.0/security/sandbox/chromium/sandbox/win/src/
H A Dpolicy_opcodes_unittest.cc347 PolicyOpcode* op1s = opcode_maker.MakeOpWStringMatch(0, txt1, kSeekForward, in TEST() local
349 ASSERT_NE(nullptr, op1s); in TEST()
354 EXPECT_EQ(EVAL_FALSE, op1s->Evaluate(&pp_tc1, 1, &mc1)); in TEST()
/dports/www/firefox-legacy/firefox-52.8.0esr/security/sandbox/chromium/sandbox/win/src/
H A Dpolicy_opcodes_unittest.cc347 PolicyOpcode* op1s = opcode_maker.MakeOpWStringMatch(0, txt1, kSeekForward, in TEST() local
349 ASSERT_NE(nullptr, op1s); in TEST()
354 EXPECT_EQ(EVAL_FALSE, op1s->Evaluate(&pp_tc1, 1, &mc1)); in TEST()
/dports/mail/thunderbird/thunderbird-91.8.0/security/sandbox/chromium/sandbox/win/src/
H A Dpolicy_opcodes_unittest.cc340 PolicyOpcode* op1s = opcode_maker.MakeOpWStringMatch( in TEST() local
342 ASSERT_NE(nullptr, op1s); in TEST()
346 EXPECT_EQ(EVAL_FALSE, op1s->Evaluate(&pp_tc1, 1, &mc1)); in TEST()
/dports/lang/spidermonkey78/firefox-78.9.0/security/sandbox/chromium/sandbox/win/src/
H A Dpolicy_opcodes_unittest.cc340 PolicyOpcode* op1s = opcode_maker.MakeOpWStringMatch( in TEST() local
342 ASSERT_NE(nullptr, op1s); in TEST()
346 EXPECT_EQ(EVAL_FALSE, op1s->Evaluate(&pp_tc1, 1, &mc1)); in TEST()
/dports/www/chromium-legacy/chromium-88.0.4324.182/sandbox/win/src/
H A Dpolicy_opcodes_unittest.cc340 PolicyOpcode* op1s = opcode_maker.MakeOpWStringMatch( in TEST() local
342 ASSERT_NE(nullptr, op1s); in TEST()
346 EXPECT_EQ(EVAL_FALSE, op1s->Evaluate(&pp_tc1, 1, &mc1)); in TEST()
/dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/config/spu/
H A Dspu.md2682 rtx op1s = gen_rtx_REG (SImode, REGNO (op1));
2691 emit_insn (gen_ashrsi3 (op0s, op1s, GEN_INT (32)));
2713 emit_insn (gen_ashrsi3 (op5, op1s, GEN_INT (31)));
/dports/lang/gcc9/gcc-9.4.0/gcc/config/spu/
H A Dspu.md2682 rtx op1s = gen_rtx_REG (SImode, REGNO (op1));
2691 emit_insn (gen_ashrsi3 (op0s, op1s, GEN_INT (32)));
2713 emit_insn (gen_ashrsi3 (op5, op1s, GEN_INT (31)));
/dports/lang/gnat_util/gcc-6-20180516/gcc/config/spu/
H A Dspu.md2673 rtx op1s = gen_rtx_REG (SImode, REGNO (op1));
2682 emit_insn (gen_ashrsi3 (op0s, op1s, GEN_INT (32)));
2704 emit_insn (gen_ashrsi3 (op5, op1s, GEN_INT (31)));
/dports/devel/riscv64-gcc/gcc-8.3.0/gcc/config/spu/
H A Dspu.md2682 rtx op1s = gen_rtx_REG (SImode, REGNO (op1));
2691 emit_insn (gen_ashrsi3 (op0s, op1s, GEN_INT (32)));
2713 emit_insn (gen_ashrsi3 (op5, op1s, GEN_INT (31)));
/dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/config/spu/
H A Dspu.md2682 rtx op1s = gen_rtx_REG (SImode, REGNO (op1));
2691 emit_insn (gen_ashrsi3 (op0s, op1s, GEN_INT (32)));
2713 emit_insn (gen_ashrsi3 (op5, op1s, GEN_INT (31)));
/dports/lang/gcc48/gcc-4.8.5/gcc/config/spu/
H A Dspu.md2673 rtx op1s = gen_rtx_REG (SImode, REGNO (op1));
2682 emit_insn (gen_ashrsi3 (op0s, op1s, GEN_INT (32)));
2704 emit_insn (gen_ashrsi3 (op5, op1s, GEN_INT (31)));
/dports/devel/mingw32-gcc/gcc-4.8.1/gcc/config/spu/
H A Dspu.md2673 rtx op1s = gen_rtx_REG (SImode, REGNO (op1));
2682 emit_insn (gen_ashrsi3 (op0s, op1s, GEN_INT (32)));
2704 emit_insn (gen_ashrsi3 (op5, op1s, GEN_INT (31)));
/dports/devel/arm-none-eabi-gcc492/gcc-4.9.2/gcc/config/spu/
H A Dspu.md2673 rtx op1s = gen_rtx_REG (SImode, REGNO (op1));
2682 emit_insn (gen_ashrsi3 (op0s, op1s, GEN_INT (32)));
2704 emit_insn (gen_ashrsi3 (op5, op1s, GEN_INT (31)));
/dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/config/spu/
H A Dspu.md2682 rtx op1s = gen_rtx_REG (SImode, REGNO (op1));
2691 emit_insn (gen_ashrsi3 (op0s, op1s, GEN_INT (32)));
2713 emit_insn (gen_ashrsi3 (op5, op1s, GEN_INT (31)));
/dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/config/spu/
H A Dspu.md2682 rtx op1s = gen_rtx_REG (SImode, REGNO (op1));
2691 emit_insn (gen_ashrsi3 (op0s, op1s, GEN_INT (32)));
2713 emit_insn (gen_ashrsi3 (op5, op1s, GEN_INT (31)));

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