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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/
H A Dreduce-or.ll10 ret i1 %or_result
23 ret i1 %or_result
40 ret i1 %or_result
65 ret i1 %or_result
91 ret i1 %or_result
101 ret i8 %or_result
111 ret i8 %or_result
127 ret i8 %or_result
151 ret i8 %or_result
176 ret i8 %or_result
[all …]
H A Dreduce-xor.ll9 %or_result = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> %a)
10 ret i1 %or_result
22 %or_result = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> %a)
23 ret i1 %or_result
39 %or_result = call i1 @llvm.vector.reduce.xor.v4i1(<4 x i1> %a)
40 ret i1 %or_result
64 %or_result = call i1 @llvm.vector.reduce.xor.v8i1(<8 x i1> %a)
65 ret i1 %or_result
90 %or_result = call i1 @llvm.vector.reduce.xor.v16i1(<16 x i1> %a)
91 ret i1 %or_result
H A Dreduce-and.ll9 %or_result = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %a)
10 ret i1 %or_result
22 %or_result = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> %a)
23 ret i1 %or_result
39 %or_result = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %a)
40 ret i1 %or_result
64 %or_result = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> %a)
65 ret i1 %or_result
90 %or_result = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> %a)
91 ret i1 %or_result
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AArch64/
H A Dreduce-or.ll10 ret i1 %or_result
23 ret i1 %or_result
40 ret i1 %or_result
65 ret i1 %or_result
91 ret i1 %or_result
101 ret i8 %or_result
111 ret i8 %or_result
127 ret i8 %or_result
151 ret i8 %or_result
176 ret i8 %or_result
[all …]
H A Dreduce-and.ll9 %or_result = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %a)
10 ret i1 %or_result
22 %or_result = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> %a)
23 ret i1 %or_result
39 %or_result = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %a)
40 ret i1 %or_result
64 %or_result = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> %a)
65 ret i1 %or_result
90 %or_result = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> %a)
91 ret i1 %or_result
H A Dreduce-xor.ll9 %or_result = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> %a)
10 ret i1 %or_result
22 %or_result = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> %a)
23 ret i1 %or_result
39 %or_result = call i1 @llvm.vector.reduce.xor.v4i1(<4 x i1> %a)
40 ret i1 %or_result
64 %or_result = call i1 @llvm.vector.reduce.xor.v8i1(<8 x i1> %a)
65 ret i1 %or_result
90 %or_result = call i1 @llvm.vector.reduce.xor.v16i1(<16 x i1> %a)
91 ret i1 %or_result
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/
H A Dreduce-or.ll10 ret i1 %or_result
23 ret i1 %or_result
40 ret i1 %or_result
65 ret i1 %or_result
91 ret i1 %or_result
101 ret i8 %or_result
111 ret i8 %or_result
127 ret i8 %or_result
151 ret i8 %or_result
176 ret i8 %or_result
[all …]
H A Dreduce-and.ll9 %or_result = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %a)
10 ret i1 %or_result
22 %or_result = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> %a)
23 ret i1 %or_result
39 %or_result = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %a)
40 ret i1 %or_result
64 %or_result = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> %a)
65 ret i1 %or_result
90 %or_result = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> %a)
91 ret i1 %or_result
H A Dreduce-xor.ll9 %or_result = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> %a)
10 ret i1 %or_result
22 %or_result = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> %a)
23 ret i1 %or_result
39 %or_result = call i1 @llvm.vector.reduce.xor.v4i1(<4 x i1> %a)
40 ret i1 %or_result
64 %or_result = call i1 @llvm.vector.reduce.xor.v8i1(<8 x i1> %a)
65 ret i1 %or_result
90 %or_result = call i1 @llvm.vector.reduce.xor.v16i1(<16 x i1> %a)
91 ret i1 %or_result
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/
H A Dreduce-or.ll10 ret i1 %or_result
23 ret i1 %or_result
40 ret i1 %or_result
65 ret i1 %or_result
91 ret i1 %or_result
101 ret i8 %or_result
111 ret i8 %or_result
127 ret i8 %or_result
151 ret i8 %or_result
176 ret i8 %or_result
[all …]
H A Dreduce-xor.ll9 %or_result = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> %a)
10 ret i1 %or_result
22 %or_result = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> %a)
23 ret i1 %or_result
39 %or_result = call i1 @llvm.vector.reduce.xor.v4i1(<4 x i1> %a)
40 ret i1 %or_result
64 %or_result = call i1 @llvm.vector.reduce.xor.v8i1(<8 x i1> %a)
65 ret i1 %or_result
90 %or_result = call i1 @llvm.vector.reduce.xor.v16i1(<16 x i1> %a)
91 ret i1 %or_result
H A Dreduce-and.ll9 %or_result = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %a)
10 ret i1 %or_result
22 %or_result = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> %a)
23 ret i1 %or_result
39 %or_result = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %a)
40 ret i1 %or_result
64 %or_result = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> %a)
65 ret i1 %or_result
90 %or_result = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> %a)
91 ret i1 %or_result
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AArch64/
H A Dreduce-or.ll17 ret i1 %or_result
40 ret i1 %or_result
73 ret i1 %or_result
126 ret i1 %or_result
203 ret i1 %or_result
219 ret i8 %or_result
235 ret i8 %or_result
266 ret i8 %or_result
317 ret i8 %or_result
370 ret i8 %or_result
[all …]
H A Dreduce-and.ll16 %or_result = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %a)
17 ret i1 %or_result
39 %or_result = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> %a)
40 ret i1 %or_result
72 %or_result = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %a)
73 ret i1 %or_result
125 %or_result = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> %a)
126 ret i1 %or_result
202 %or_result = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> %a)
203 ret i1 %or_result
H A Dreduce-xor.ll15 %or_result = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> %a)
16 ret i1 %or_result
38 %or_result = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> %a)
39 ret i1 %or_result
71 %or_result = call i1 @llvm.vector.reduce.xor.v4i1(<4 x i1> %a)
72 ret i1 %or_result
124 %or_result = call i1 @llvm.vector.reduce.xor.v8i1(<8 x i1> %a)
125 ret i1 %or_result
201 %or_result = call i1 @llvm.vector.reduce.xor.v16i1(<16 x i1> %a)
202 ret i1 %or_result
/dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/issue30/
H A Dalu.vhdl159 or_result <= operand1 or operand2;
161 output <= or_result;
162 flags_out <= ( sign_bit => or_result(7),
164 zero_bit => not (or_result(7) or or_result(6) or or_result(5) or or_result(4) or
165 or_result(3) or or_result(2) or or_result(1) or or_result(0)),
166 parity_overflow_bit => not (or_result(7) xor or_result(6) xor or_result(5) xor
167 or_result(4) xor or_result(3) xor or_result(2) xor
168 or_result(1) xor or_result(0)),
1253 data6 => or_result, -- or
1270 data22 => or_result, -- SET
[all …]
/dports/net/freeradius3/freeradius-server-3.0.25/src/modules/rlm_ippool/
H A Drlm_ippool.c158 uint32_t or_result; in mod_instantiate() local
239 or_result = i | inst->netmask; in mod_instantiate()
240 if (~inst->netmask != 0 && (or_result == inst->netmask || (~or_result == 0))) { in mod_instantiate()
/dports/multimedia/gstreamer1-plugins-svt-hevc/SVT-HEVC-1.5.1/Source/Lib/ASM_SSE2/
H A DEbApplySaoLcu16bit_Intrinsic_SSE2.c28 …__m128i boIdx_sub_saoBandPosn, cmp_result, cmp_result1, cmp_result2, cmp_result3, or_result, resul… in SAOApplyBO16bit_SSE2_INTRIN() local
59 …or_result = _mm_or_si128(_mm_or_si128(cmp_result, cmp_result1), _mm_or_si128(cmp_result2, cmp_resu… in SAOApplyBO16bit_SSE2_INTRIN()
62 …_mm_min_epi16(_mm_add_epi16(rec_0_7, _mm_unpacklo_epi8(or_result, _mm_cmpgt_epi8(xmm_0, or_result)… in SAOApplyBO16bit_SSE2_INTRIN()
63 …mm_min_epi16(_mm_add_epi16(rec_8_15, _mm_unpackhi_epi8(or_result, _mm_cmpgt_epi8(xmm_0, or_result)… in SAOApplyBO16bit_SSE2_INTRIN()
/dports/multimedia/svt-hevc/SVT-HEVC-1.5.1/Source/Lib/ASM_SSE2/
H A DEbApplySaoLcu16bit_Intrinsic_SSE2.c28 …__m128i boIdx_sub_saoBandPosn, cmp_result, cmp_result1, cmp_result2, cmp_result3, or_result, resul… in SAOApplyBO16bit_SSE2_INTRIN() local
59 …or_result = _mm_or_si128(_mm_or_si128(cmp_result, cmp_result1), _mm_or_si128(cmp_result2, cmp_resu… in SAOApplyBO16bit_SSE2_INTRIN()
62 …_mm_min_epi16(_mm_add_epi16(rec_0_7, _mm_unpacklo_epi8(or_result, _mm_cmpgt_epi8(xmm_0, or_result)… in SAOApplyBO16bit_SSE2_INTRIN()
63 …mm_min_epi16(_mm_add_epi16(rec_8_15, _mm_unpackhi_epi8(or_result, _mm_cmpgt_epi8(xmm_0, or_result)… in SAOApplyBO16bit_SSE2_INTRIN()
/dports/shells/fish/fish-3.3.1/src/
H A Dbuiltin_test.cpp631 bool or_result = false; in evaluate() local
633 if (or_result) { // short circuit in evaluate()
653 or_result = or_result || and_result; in evaluate()
655 return or_result; in evaluate()
/dports/science/py-scoria/scoria-1.0.5/scoria/dumbpy/
H A DUtils.py112 or_result = [x or y for x,y in zip(arr1, arr2)]
113 return array(or_result)
/dports/emulators/mess/mame-mame0226/3rdparty/bgfx/3rdparty/spirv-tools/source/opt/
H A Damd_ext_to_khr.cpp374 Instruction* or_result = ir_builder.AddBinaryOp( in ReplaceSwizzleInvocationsMasked() local
377 uint_type_id, SpvOpBitwiseXor, or_result->result_id(), uint_z); in ReplaceSwizzleInvocationsMasked()
/dports/emulators/mame/mame-mame0226/3rdparty/bgfx/3rdparty/spirv-tools/source/opt/
H A Damd_ext_to_khr.cpp374 Instruction* or_result = ir_builder.AddBinaryOp( in ReplaceSwizzleInvocationsMasked() local
377 uint_type_id, SpvOpBitwiseXor, or_result->result_id(), uint_z); in ReplaceSwizzleInvocationsMasked()
/dports/www/qt5-webengine/qtwebengine-everywhere-src-5.15.2/src/3rdparty/chromium/third_party/SPIRV-Tools/src/source/opt/
H A Damd_ext_to_khr.cpp368 Instruction* or_result = ir_builder.AddBinaryOp( in ReplaceSwizzleInvocationsMasked() local
371 uint_type_id, SpvOpBitwiseXor, or_result->result_id(), uint_z); in ReplaceSwizzleInvocationsMasked()
/dports/devel/intel-graphics-compiler/SPIRV-Tools/source/opt/
H A Damd_ext_to_khr.cpp368 Instruction* or_result = ir_builder.AddBinaryOp( in ReplaceSwizzleInvocationsMasked() local
371 uint_type_id, SpvOpBitwiseXor, or_result->result_id(), uint_z); in ReplaceSwizzleInvocationsMasked()

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