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Searched refs:paren_levels (Results 1 – 5 of 5) sorted by relevance

/dports/math/openfst/openfst-1.8.1/src/include/fst/extensions/mpdt/
H A Dinfo.h98 std::unordered_map<Label, int> paren_levels; in MPdtInfo() local
116 paren_levels[pair.first] = level; in MPdtInfo()
117 paren_levels[pair.second] = level; in MPdtInfo()
139 const auto level = paren_levels[arc.ilabel]; in MPdtInfo()
/dports/math/scilab/scilab-6.1.1/scilab/modules/ast/src/cpp/parse/
H A Dscanscilab.cpp1953 static std::stack<int> paren_levels; variable
2651 paren_levels.push(0);
2817 paren_levels.push(0);
3056 ++paren_levels.top();
3063 --paren_levels.top();
3120 paren_levels.pop();
3129 paren_levels.pop();
3208 && paren_levels.top() == 0)
3244 && paren_levels.top() == 0)
3330 paren_levels.pop();
/dports/math/scilab/scilab-6.1.1/scilab/modules/ast/src/cpp/parse/flex/
H A Dscanscilab.ll32 static std::stack<int> paren_levels;
446 paren_levels.push(0);
545 paren_levels.push(0);
747 ++paren_levels.top();
752 --paren_levels.top();
798 paren_levels.pop();
805 paren_levels.pop();
878 && paren_levels.top() == 0)
912 && paren_levels.top() == 0)
988 paren_levels.pop();
/dports/cad/iverilog/verilog-11.0/tgt-vhdl/
H A Dvhdl_syntax.cc882 int vhdl_expr::paren_levels(0); member in vhdl_expr
886 if (paren_levels++ > 0) in open_parens()
892 assert(paren_levels > 0); in close_parens()
894 if (--paren_levels > 0) in close_parens()
H A Dvhdl_syntax.hh61 static int paren_levels; member in vhdl_expr