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Searched refs:phydev_err (Results 1 – 25 of 51) sorted by relevance

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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/net/phy/
H A Dnxp-c45-tja11xx.c369 phydev_err(phydev, "delay value smaller than %u\n", MIN_ID_PS); in nxp_c45_check_delay()
374 phydev_err(phydev, "delay value higher than %u\n", MAX_ID_PS); in nxp_c45_check_delay()
441 phydev_err(phydev, in nxp_c45_get_delays()
457 phydev_err(phydev, in nxp_c45_get_delays()
476 phydev_err(phydev, "rgmii mode not supported\n"); in nxp_c45_set_phy_mode()
487 phydev_err(phydev, "rgmii-id, rgmii-txid, rgmii-rxid modes are not supported\n"); in nxp_c45_set_phy_mode()
500 phydev_err(phydev, "mii mode not supported\n"); in nxp_c45_set_phy_mode()
508 phydev_err(phydev, "rev-mii mode not supported\n"); in nxp_c45_set_phy_mode()
516 phydev_err(phydev, "rmii mode not supported\n"); in nxp_c45_set_phy_mode()
524 phydev_err(phydev, "sgmii mode not supported\n"); in nxp_c45_set_phy_mode()
[all …]
H A Ddp83867.c432 phydev_err(phydev, in dp83867_set_downshift()
508 phydev_err(phydev, "ti,rx-internal-delay must be specified\n"); in dp83867_verify_rgmii_cfg()
516 phydev_err(phydev, "ti,tx-internal-delay must be specified\n"); in dp83867_verify_rgmii_cfg()
545 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n", in dp83867_of_init()
568 phydev_err(phydev, in dp83867_of_init()
578 phydev_err(phydev, in dp83867_of_init()
601 phydev_err(phydev, "tx-fifo-depth value %u out of range\n", in dp83867_of_init()
612 phydev_err(phydev, "rx-fifo-depth value %u out of range\n", in dp83867_of_init()
H A Dat803x.c431 phydev_err(phydev, "failed to register VDDIO regulator\n"); in at8031_register_regulators()
437 phydev_err(phydev, "failed to register VDDH regulator\n"); in at8031_register_regulators()
466 phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n"); in at803x_parse_dt()
474 phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n"); in at803x_parse_dt()
496 phydev_err(phydev, "invalid qca,clk-out-frequency\n"); in at803x_parse_dt()
535 phydev_err(phydev, "invalid qca,clk-out-strength\n"); in at803x_parse_dt()
554 phydev_err(phydev, "failed to get VDDIO regulator\n"); in at803x_parse_dt()
H A Ddp83869.c350 phydev_err(phydev, "Failed to read RX CFG\n"); in dp83869_get_wol()
367 phydev_err(phydev, "Failed to read RX SOP 1\n"); in dp83869_get_wol()
377 phydev_err(phydev, "Failed to read RX SOP 2\n"); in dp83869_get_wol()
387 phydev_err(phydev, "Failed to read RX SOP 3\n"); in dp83869_get_wol()
459 phydev_err(phydev, in dp83869_set_downshift()
H A Dmicrel.c260 phydev_err(phydev, "failed to set led mode\n"); in kszphy_setup_led()
279 phydev_err(phydev, "failed to disable broadcast address\n"); in kszphy_broadcast_disable()
299 phydev_err(phydev, "failed to disable NAND tree mode\n"); in kszphy_nand_tree_disable()
313 phydev_err(phydev, in kszphy_config_reset()
803 phydev_err(phydev, "failed to force the phy to master mode\n"); in ksz9031_config_init()
1155 phydev_err(phydev, "invalid led mode: 0x%02x\n", in kszphy_probe()
1178 phydev_err(phydev, "Clock rate out of range: %ld\n", in kszphy_probe()
H A Dcortina.c68 phydev_err(phydev, "Error matching phy with %s driver\n", in cortina_probe()
H A Dphy_device.c559 phydev_err(dev, "error %d loading PHY driver module for ID 0x%08lx\n", in phy_request_driver_module()
895 phydev_err(phydev, "failed to initialize\n"); in phy_device_register()
901 phydev_err(phydev, "failed to add\n"); in phy_device_register()
1330 phydev_err(phydev, "failed to get the bus module\n"); in phy_attach_direct()
1349 phydev_err(phydev, "failed to get the device driver module\n"); in phy_attach_direct()
1396 phydev_err(phydev, "error creating 'phy_standalone' sysfs entry\n"); in phy_attach_direct()
2278 phydev_err(phydev, "Master/Slave resolution failed, maybe conflicting manual settings?\n"); in genphy_read_lpa()
2280 phydev_err(phydev, "Master/Slave resolution failed\n"); in genphy_read_lpa()
2832 phydev_err(phydev, "Delay %d is out of range\n", delay); in phy_get_internal_delay()
2854 phydev_err(phydev, "error finding internal delay index for %d\n", in phy_get_internal_delay()
H A Drockchip.c116 phydev_err(phydev, "rockchip_integrated_phy_analog_init err: %d.\n", in rockchip_link_change_notify()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/net/phy/
H A Dnxp-c45-tja11xx.c369 phydev_err(phydev, "delay value smaller than %u\n", MIN_ID_PS); in nxp_c45_check_delay()
374 phydev_err(phydev, "delay value higher than %u\n", MAX_ID_PS); in nxp_c45_check_delay()
441 phydev_err(phydev, in nxp_c45_get_delays()
457 phydev_err(phydev, in nxp_c45_get_delays()
476 phydev_err(phydev, "rgmii mode not supported\n"); in nxp_c45_set_phy_mode()
487 phydev_err(phydev, "rgmii-id, rgmii-txid, rgmii-rxid modes are not supported\n"); in nxp_c45_set_phy_mode()
500 phydev_err(phydev, "mii mode not supported\n"); in nxp_c45_set_phy_mode()
508 phydev_err(phydev, "rev-mii mode not supported\n"); in nxp_c45_set_phy_mode()
516 phydev_err(phydev, "rmii mode not supported\n"); in nxp_c45_set_phy_mode()
524 phydev_err(phydev, "sgmii mode not supported\n"); in nxp_c45_set_phy_mode()
[all …]
H A Ddp83867.c432 phydev_err(phydev, in dp83867_set_downshift()
508 phydev_err(phydev, "ti,rx-internal-delay must be specified\n"); in dp83867_verify_rgmii_cfg()
516 phydev_err(phydev, "ti,tx-internal-delay must be specified\n"); in dp83867_verify_rgmii_cfg()
545 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n", in dp83867_of_init()
568 phydev_err(phydev, in dp83867_of_init()
578 phydev_err(phydev, in dp83867_of_init()
601 phydev_err(phydev, "tx-fifo-depth value %u out of range\n", in dp83867_of_init()
612 phydev_err(phydev, "rx-fifo-depth value %u out of range\n", in dp83867_of_init()
H A Dat803x.c431 phydev_err(phydev, "failed to register VDDIO regulator\n"); in at8031_register_regulators()
437 phydev_err(phydev, "failed to register VDDH regulator\n"); in at8031_register_regulators()
466 phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n"); in at803x_parse_dt()
474 phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n"); in at803x_parse_dt()
496 phydev_err(phydev, "invalid qca,clk-out-frequency\n"); in at803x_parse_dt()
535 phydev_err(phydev, "invalid qca,clk-out-strength\n"); in at803x_parse_dt()
554 phydev_err(phydev, "failed to get VDDIO regulator\n"); in at803x_parse_dt()
H A Ddp83869.c350 phydev_err(phydev, "Failed to read RX CFG\n"); in dp83869_get_wol()
367 phydev_err(phydev, "Failed to read RX SOP 1\n"); in dp83869_get_wol()
377 phydev_err(phydev, "Failed to read RX SOP 2\n"); in dp83869_get_wol()
387 phydev_err(phydev, "Failed to read RX SOP 3\n"); in dp83869_get_wol()
459 phydev_err(phydev, in dp83869_set_downshift()
H A Dmicrel.c260 phydev_err(phydev, "failed to set led mode\n"); in kszphy_setup_led()
279 phydev_err(phydev, "failed to disable broadcast address\n"); in kszphy_broadcast_disable()
299 phydev_err(phydev, "failed to disable NAND tree mode\n"); in kszphy_nand_tree_disable()
313 phydev_err(phydev, in kszphy_config_reset()
803 phydev_err(phydev, "failed to force the phy to master mode\n"); in ksz9031_config_init()
1155 phydev_err(phydev, "invalid led mode: 0x%02x\n", in kszphy_probe()
1178 phydev_err(phydev, "Clock rate out of range: %ld\n", in kszphy_probe()
H A Dcortina.c68 phydev_err(phydev, "Error matching phy with %s driver\n", in cortina_probe()
H A Dphy_device.c559 phydev_err(dev, "error %d loading PHY driver module for ID 0x%08lx\n", in phy_request_driver_module()
895 phydev_err(phydev, "failed to initialize\n"); in phy_device_register()
901 phydev_err(phydev, "failed to add\n"); in phy_device_register()
1330 phydev_err(phydev, "failed to get the bus module\n"); in phy_attach_direct()
1349 phydev_err(phydev, "failed to get the device driver module\n"); in phy_attach_direct()
1396 phydev_err(phydev, "error creating 'phy_standalone' sysfs entry\n"); in phy_attach_direct()
2278 phydev_err(phydev, "Master/Slave resolution failed, maybe conflicting manual settings?\n"); in genphy_read_lpa()
2280 phydev_err(phydev, "Master/Slave resolution failed\n"); in genphy_read_lpa()
2832 phydev_err(phydev, "Delay %d is out of range\n", delay); in phy_get_internal_delay()
2854 phydev_err(phydev, "error finding internal delay index for %d\n", in phy_get_internal_delay()
H A Drockchip.c116 phydev_err(phydev, "rockchip_integrated_phy_analog_init err: %d.\n", in rockchip_link_change_notify()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/net/phy/
H A Dnxp-c45-tja11xx.c369 phydev_err(phydev, "delay value smaller than %u\n", MIN_ID_PS); in nxp_c45_check_delay()
374 phydev_err(phydev, "delay value higher than %u\n", MAX_ID_PS); in nxp_c45_check_delay()
441 phydev_err(phydev, in nxp_c45_get_delays()
457 phydev_err(phydev, in nxp_c45_get_delays()
476 phydev_err(phydev, "rgmii mode not supported\n"); in nxp_c45_set_phy_mode()
487 phydev_err(phydev, "rgmii-id, rgmii-txid, rgmii-rxid modes are not supported\n"); in nxp_c45_set_phy_mode()
500 phydev_err(phydev, "mii mode not supported\n"); in nxp_c45_set_phy_mode()
508 phydev_err(phydev, "rev-mii mode not supported\n"); in nxp_c45_set_phy_mode()
516 phydev_err(phydev, "rmii mode not supported\n"); in nxp_c45_set_phy_mode()
524 phydev_err(phydev, "sgmii mode not supported\n"); in nxp_c45_set_phy_mode()
[all …]
H A Ddp83867.c432 phydev_err(phydev, in dp83867_set_downshift()
508 phydev_err(phydev, "ti,rx-internal-delay must be specified\n"); in dp83867_verify_rgmii_cfg()
516 phydev_err(phydev, "ti,tx-internal-delay must be specified\n"); in dp83867_verify_rgmii_cfg()
545 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n", in dp83867_of_init()
568 phydev_err(phydev, in dp83867_of_init()
578 phydev_err(phydev, in dp83867_of_init()
601 phydev_err(phydev, "tx-fifo-depth value %u out of range\n", in dp83867_of_init()
612 phydev_err(phydev, "rx-fifo-depth value %u out of range\n", in dp83867_of_init()
H A Dat803x.c431 phydev_err(phydev, "failed to register VDDIO regulator\n"); in at8031_register_regulators()
437 phydev_err(phydev, "failed to register VDDH regulator\n"); in at8031_register_regulators()
466 phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n"); in at803x_parse_dt()
474 phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n"); in at803x_parse_dt()
496 phydev_err(phydev, "invalid qca,clk-out-frequency\n"); in at803x_parse_dt()
535 phydev_err(phydev, "invalid qca,clk-out-strength\n"); in at803x_parse_dt()
554 phydev_err(phydev, "failed to get VDDIO regulator\n"); in at803x_parse_dt()
H A Ddp83869.c350 phydev_err(phydev, "Failed to read RX CFG\n"); in dp83869_get_wol()
367 phydev_err(phydev, "Failed to read RX SOP 1\n"); in dp83869_get_wol()
377 phydev_err(phydev, "Failed to read RX SOP 2\n"); in dp83869_get_wol()
387 phydev_err(phydev, "Failed to read RX SOP 3\n"); in dp83869_get_wol()
459 phydev_err(phydev, in dp83869_set_downshift()
H A Dmicrel.c260 phydev_err(phydev, "failed to set led mode\n"); in kszphy_setup_led()
279 phydev_err(phydev, "failed to disable broadcast address\n"); in kszphy_broadcast_disable()
299 phydev_err(phydev, "failed to disable NAND tree mode\n"); in kszphy_nand_tree_disable()
313 phydev_err(phydev, in kszphy_config_reset()
803 phydev_err(phydev, "failed to force the phy to master mode\n"); in ksz9031_config_init()
1155 phydev_err(phydev, "invalid led mode: 0x%02x\n", in kszphy_probe()
1178 phydev_err(phydev, "Clock rate out of range: %ld\n", in kszphy_probe()
H A Dcortina.c68 phydev_err(phydev, "Error matching phy with %s driver\n", in cortina_probe()
H A Dphy_device.c559 phydev_err(dev, "error %d loading PHY driver module for ID 0x%08lx\n", in phy_request_driver_module()
895 phydev_err(phydev, "failed to initialize\n"); in phy_device_register()
901 phydev_err(phydev, "failed to add\n"); in phy_device_register()
1330 phydev_err(phydev, "failed to get the bus module\n"); in phy_attach_direct()
1349 phydev_err(phydev, "failed to get the device driver module\n"); in phy_attach_direct()
1396 phydev_err(phydev, "error creating 'phy_standalone' sysfs entry\n"); in phy_attach_direct()
2278 phydev_err(phydev, "Master/Slave resolution failed, maybe conflicting manual settings?\n"); in genphy_read_lpa()
2280 phydev_err(phydev, "Master/Slave resolution failed\n"); in genphy_read_lpa()
2832 phydev_err(phydev, "Delay %d is out of range\n", delay); in phy_get_internal_delay()
2854 phydev_err(phydev, "error finding internal delay index for %d\n", in phy_get_internal_delay()
H A Drockchip.c116 phydev_err(phydev, "rockchip_integrated_phy_analog_init err: %d.\n", in rockchip_link_change_notify()
/dports/multimedia/libv4l/linux-5.13-rc2/include/linux/
H A Dphy.h963 phydev_err(phydev, "%s failed: %d\n", __func__, __ret); \
1061 phydev_err(phydev, "%s failed: %d\n", __func__, __ret); \
1455 #define phydev_err(_phydev, format, args...) \ macro

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