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/dports/multimedia/libv4l/linux-5.13-rc2/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun4i-a10-mod1-clk.yaml44 #include <dt-bindings/clock/sun4i-a10-pll2.h>
50 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
51 <&pll2 SUN4I_A10_PLL2_4X>,
52 <&pll2 SUN4I_A10_PLL2_2X>,
53 <&pll2 SUN4I_A10_PLL2_1X>;
H A Drenesas,cpg-clocks.yaml76 - const: pll2
202 - const: pll2
/dports/multimedia/v4l-utils/linux-5.13-rc2/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun4i-a10-mod1-clk.yaml44 #include <dt-bindings/clock/sun4i-a10-pll2.h>
50 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
51 <&pll2 SUN4I_A10_PLL2_4X>,
52 <&pll2 SUN4I_A10_PLL2_2X>,
53 <&pll2 SUN4I_A10_PLL2_1X>;
H A Drenesas,cpg-clocks.yaml76 - const: pll2
202 - const: pll2
/dports/multimedia/v4l_compat/linux-5.13-rc2/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun4i-a10-mod1-clk.yaml44 #include <dt-bindings/clock/sun4i-a10-pll2.h>
50 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
51 <&pll2 SUN4I_A10_PLL2_4X>,
52 <&pll2 SUN4I_A10_PLL2_2X>,
53 <&pll2 SUN4I_A10_PLL2_1X>;
H A Drenesas,cpg-clocks.yaml76 - const: pll2
202 - const: pll2
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/mfd/
H A Dsm501.c121 pll2 = 288 * MHZ; in decode_div()
123 return pll2 / div_tab[(val >> lshft) & mask]; in decode_div()
140 unsigned long pll2 = 0; in sm501_dump_clk() local
144 pll2 = 336 * MHZ; in sm501_dump_clk()
147 pll2 = 288 * MHZ; in sm501_dump_clk()
150 pll2 = 240 * MHZ; in sm501_dump_clk()
153 pll2 = 192 * MHZ; in sm501_dump_clk()
157 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
160 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
167 fmt_freq(pll2), sdclk0, sdclk1); in sm501_dump_clk()
[all …]
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/mfd/
H A Dsm501.c121 pll2 = 288 * MHZ; in decode_div()
123 return pll2 / div_tab[(val >> lshft) & mask]; in decode_div()
140 unsigned long pll2 = 0; in sm501_dump_clk() local
144 pll2 = 336 * MHZ; in sm501_dump_clk()
147 pll2 = 288 * MHZ; in sm501_dump_clk()
150 pll2 = 240 * MHZ; in sm501_dump_clk()
153 pll2 = 192 * MHZ; in sm501_dump_clk()
157 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
160 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
167 fmt_freq(pll2), sdclk0, sdclk1); in sm501_dump_clk()
[all …]
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/mfd/
H A Dsm501.c121 pll2 = 288 * MHZ; in decode_div()
123 return pll2 / div_tab[(val >> lshft) & mask]; in decode_div()
140 unsigned long pll2 = 0; in sm501_dump_clk() local
144 pll2 = 336 * MHZ; in sm501_dump_clk()
147 pll2 = 288 * MHZ; in sm501_dump_clk()
150 pll2 = 240 * MHZ; in sm501_dump_clk()
153 pll2 = 192 * MHZ; in sm501_dump_clk()
157 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
160 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
167 fmt_freq(pll2), sdclk0, sdclk1); in sm501_dump_clk()
[all …]
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32H7xx_HAL_Driver/src/
H A Dstm32h7xx_hal_rcc_ex.c2694 assert_param(IS_RCC_PLL2M_VALUE(pll2->PLL2M)); in RCCEx_PLL2_Config()
2695 assert_param(IS_RCC_PLL2N_VALUE(pll2->PLL2N)); in RCCEx_PLL2_Config()
2696 assert_param(IS_RCC_PLL2P_VALUE(pll2->PLL2P)); in RCCEx_PLL2_Config()
2697 assert_param(IS_RCC_PLL2R_VALUE(pll2->PLL2R)); in RCCEx_PLL2_Config()
2728 __HAL_RCC_PLL2_CONFIG(pll2->PLL2M, in RCCEx_PLL2_Config()
2729 pll2->PLL2N, in RCCEx_PLL2_Config()
2730 pll2->PLL2P, in RCCEx_PLL2_Config()
2731 pll2->PLL2Q, in RCCEx_PLL2_Config()
2732 pll2->PLL2R); in RCCEx_PLL2_Config()
2735 __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ; in RCCEx_PLL2_Config()
[all …]
/dports/misc/rump/buildrump.sh-b914579/src/sys/external/bsd/drm2/dist/drm/nouveau/core/subdev/devinit/
H A Dnouveau_subdev_devinit_nv04.c211 uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2; in setPLL_double_highregs() local
221 pll2 = 0; in setPLL_double_highregs()
230 pll2 |= 0x011f; in setPLL_double_highregs()
236 if (oldpll1 == pll1 && oldpll2 == pll2) in setPLL_double_highregs()
273 nv_wr32(devinit, reg2, pll2); in setPLL_double_highregs()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/hisilicon/hibmc/
H A Dhibmc_drm_de.c285 static void get_pll_config(u64 x, u64 y, u32 *pll1, u32 *pll2) in get_pll_config() argument
294 *pll2 = hibmc_pll_table[i].pll2_config_value; in get_pll_config()
301 *pll2 = CRT_PLL2_HS_25MHZ; in get_pll_config()
317 u32 pll2; /* bit[63:32] of PLL */ in display_ctrl_adjust() local
323 get_pll_config(x, y, &pll1, &pll2); in display_ctrl_adjust()
324 writel(pll2, priv->mmio + CRT_PLL2_HS); in display_ctrl_adjust()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/hisilicon/hibmc/
H A Dhibmc_drm_de.c285 static void get_pll_config(u64 x, u64 y, u32 *pll1, u32 *pll2) in get_pll_config() argument
294 *pll2 = hibmc_pll_table[i].pll2_config_value; in get_pll_config()
301 *pll2 = CRT_PLL2_HS_25MHZ; in get_pll_config()
317 u32 pll2; /* bit[63:32] of PLL */ in display_ctrl_adjust() local
323 get_pll_config(x, y, &pll1, &pll2); in display_ctrl_adjust()
324 writel(pll2, priv->mmio + CRT_PLL2_HS); in display_ctrl_adjust()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/hisilicon/hibmc/
H A Dhibmc_drm_de.c285 static void get_pll_config(u64 x, u64 y, u32 *pll1, u32 *pll2) in get_pll_config() argument
294 *pll2 = hibmc_pll_table[i].pll2_config_value; in get_pll_config()
301 *pll2 = CRT_PLL2_HS_25MHZ; in get_pll_config()
317 u32 pll2; /* bit[63:32] of PLL */ in display_ctrl_adjust() local
323 get_pll_config(x, y, &pll1, &pll2); in display_ctrl_adjust()
324 writel(pll2, priv->mmio + CRT_PLL2_HS); in display_ctrl_adjust()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dnv04.c208 uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2; in setPLL_double_highregs() local
218 pll2 = 0; in setPLL_double_highregs()
227 pll2 |= 0x011f; in setPLL_double_highregs()
233 if (oldpll1 == pll1 && oldpll2 == pll2) in setPLL_double_highregs()
266 nvkm_wr32(device, reg2, pll2); in setPLL_double_highregs()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dnv04.c208 uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2; in setPLL_double_highregs() local
218 pll2 = 0; in setPLL_double_highregs()
227 pll2 |= 0x011f; in setPLL_double_highregs()
233 if (oldpll1 == pll1 && oldpll2 == pll2) in setPLL_double_highregs()
266 nvkm_wr32(device, reg2, pll2); in setPLL_double_highregs()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dnv04.c208 uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2; in setPLL_double_highregs() local
218 pll2 = 0; in setPLL_double_highregs()
227 pll2 |= 0x011f; in setPLL_double_highregs()
233 if (oldpll1 == pll1 && oldpll2 == pll2) in setPLL_double_highregs()
266 nvkm_wr32(device, reg2, pll2); in setPLL_double_highregs()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/nouveau/dispnv04/
H A Dhw.c133 uint32_t pll2, struct nvkm_pll_vals *pllvals) in nouveau_hw_decode_pll() argument
144 pllvals->NM1 = pll2 & 0xffff; in nouveau_hw_decode_pll()
147 pllvals->NM2 = pll2 >> 16; in nouveau_hw_decode_pll()
150 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2) in nouveau_hw_decode_pll()
151 pllvals->NM2 = pll2 & 0xffff; in nouveau_hw_decode_pll()
170 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
180 pll2 = nvif_rd32(device, reg1 + 4); in nouveau_hw_get_pllvals()
184 pll2 = nvif_rd32(device, reg2); in nouveau_hw_get_pllvals()
193 pll2 = 0; in nouveau_hw_get_pllvals()
196 pll2 = 0; in nouveau_hw_get_pllvals()
[all …]
/dports/misc/rump/buildrump.sh-b914579/src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv04/
H A Dnouveau_dispnv04_hw.c141 uint32_t pll2, struct nouveau_pll_vals *pllvals) in nouveau_hw_decode_pll() argument
152 pllvals->NM1 = pll2 & 0xffff; in nouveau_hw_decode_pll()
155 pllvals->NM2 = pll2 >> 16; in nouveau_hw_decode_pll()
158 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2) in nouveau_hw_decode_pll()
159 pllvals->NM2 = pll2 & 0xffff; in nouveau_hw_decode_pll()
178 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
188 pll2 = nv_rd32(device, reg1 + 4); in nouveau_hw_get_pllvals()
192 pll2 = nv_rd32(device, reg2); in nouveau_hw_get_pllvals()
201 pll2 = 0; in nouveau_hw_get_pllvals()
204 pll2 = 0; in nouveau_hw_get_pllvals()
[all …]
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/nouveau/dispnv04/
H A Dhw.c133 uint32_t pll2, struct nvkm_pll_vals *pllvals) in nouveau_hw_decode_pll() argument
144 pllvals->NM1 = pll2 & 0xffff; in nouveau_hw_decode_pll()
147 pllvals->NM2 = pll2 >> 16; in nouveau_hw_decode_pll()
150 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2) in nouveau_hw_decode_pll()
151 pllvals->NM2 = pll2 & 0xffff; in nouveau_hw_decode_pll()
170 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
180 pll2 = nvif_rd32(device, reg1 + 4); in nouveau_hw_get_pllvals()
184 pll2 = nvif_rd32(device, reg2); in nouveau_hw_get_pllvals()
193 pll2 = 0; in nouveau_hw_get_pllvals()
196 pll2 = 0; in nouveau_hw_get_pllvals()
[all …]
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/nouveau/dispnv04/
H A Dhw.c133 uint32_t pll2, struct nvkm_pll_vals *pllvals) in nouveau_hw_decode_pll() argument
144 pllvals->NM1 = pll2 & 0xffff; in nouveau_hw_decode_pll()
147 pllvals->NM2 = pll2 >> 16; in nouveau_hw_decode_pll()
150 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2) in nouveau_hw_decode_pll()
151 pllvals->NM2 = pll2 & 0xffff; in nouveau_hw_decode_pll()
170 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
180 pll2 = nvif_rd32(device, reg1 + 4); in nouveau_hw_get_pllvals()
184 pll2 = nvif_rd32(device, reg2); in nouveau_hw_get_pllvals()
193 pll2 = 0; in nouveau_hw_get_pllvals()
196 pll2 = 0; in nouveau_hw_get_pllvals()
[all …]
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/tegra/
H A Dsor.c367 unsigned int pll2; member
1450 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1452 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1460 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1463 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
2286 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2288 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
3287 .pll2 = 0x19,
3459 .pll2 = 0x19,
3520 .pll2 = 0x165,
[all …]
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/tegra/
H A Dsor.c367 unsigned int pll2; member
1450 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1452 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1460 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1463 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
2286 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2288 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
3287 .pll2 = 0x19,
3459 .pll2 = 0x19,
3520 .pll2 = 0x165,
[all …]
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/tegra/
H A Dsor.c367 unsigned int pll2; member
1450 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1452 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1460 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1463 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
2286 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2288 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
3287 .pll2 = 0x19,
3459 .pll2 = 0x19,
3520 .pll2 = 0x165,
[all …]
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/clk/sunxi/
H A DMakefile12 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a10-pll2.o

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