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Searched refs:pll_cfg1 (Results 1 – 25 of 62) sorted by relevance

123

/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/mach-imx/imx8m/
H A Dclock.c20 u32 pll_cfg0, pll_cfg1, pllout; in decode_frac_pll() local
28 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); in decode_frac_pll()
80 u32 pll_cfg0, pll_cfg1, pll_cfg2; in decode_sscg_pll() local
234 sse = pll_cfg1 & SSCG_PLL_SSE_MASK; in decode_sscg_pll()
660 pll_cfg1 = &ana_pll->arm_pll_cfg1; in frac_pll_init()
678 writel(val_cfg1, pll_cfg1); in frac_pll_init()
702 pll_cfg1 = &ana_pll->sys_pll1_cfg1; in sscg_pll_init()
717 pll_cfg1 = &ana_pll->sys_pll2_cfg1; in sscg_pll_init()
732 pll_cfg1 = &ana_pll->sys_pll3_cfg1; in sscg_pll_init()
749 writel(val_cfg1, pll_cfg1); in sscg_pll_init()
[all …]
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/mach-imx/imx8m/
H A Dclock.c20 u32 pll_cfg0, pll_cfg1, pllout; in decode_frac_pll() local
28 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); in decode_frac_pll()
80 u32 pll_cfg0, pll_cfg1, pll_cfg2; in decode_sscg_pll() local
234 sse = pll_cfg1 & SSCG_PLL_SSE_MASK; in decode_sscg_pll()
660 pll_cfg1 = &ana_pll->arm_pll_cfg1; in frac_pll_init()
678 writel(val_cfg1, pll_cfg1); in frac_pll_init()
702 pll_cfg1 = &ana_pll->sys_pll1_cfg1; in sscg_pll_init()
717 pll_cfg1 = &ana_pll->sys_pll2_cfg1; in sscg_pll_init()
732 pll_cfg1 = &ana_pll->sys_pll3_cfg1; in sscg_pll_init()
749 writel(val_cfg1, pll_cfg1); in sscg_pll_init()
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/mach-imx/imx8m/
H A Dclock.c20 u32 pll_cfg0, pll_cfg1, pllout; in decode_frac_pll() local
28 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); in decode_frac_pll()
80 u32 pll_cfg0, pll_cfg1, pll_cfg2; in decode_sscg_pll() local
234 sse = pll_cfg1 & SSCG_PLL_SSE_MASK; in decode_sscg_pll()
660 pll_cfg1 = &ana_pll->arm_pll_cfg1; in frac_pll_init()
678 writel(val_cfg1, pll_cfg1); in frac_pll_init()
702 pll_cfg1 = &ana_pll->sys_pll1_cfg1; in sscg_pll_init()
717 pll_cfg1 = &ana_pll->sys_pll2_cfg1; in sscg_pll_init()
732 pll_cfg1 = &ana_pll->sys_pll3_cfg1; in sscg_pll_init()
749 writel(val_cfg1, pll_cfg1); in sscg_pll_init()
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/mach-imx/imx8m/
H A Dclock.c20 u32 pll_cfg0, pll_cfg1, pllout; in decode_frac_pll() local
28 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); in decode_frac_pll()
80 u32 pll_cfg0, pll_cfg1, pll_cfg2; in decode_sscg_pll() local
234 sse = pll_cfg1 & SSCG_PLL_SSE_MASK; in decode_sscg_pll()
660 pll_cfg1 = &ana_pll->arm_pll_cfg1; in frac_pll_init()
678 writel(val_cfg1, pll_cfg1); in frac_pll_init()
702 pll_cfg1 = &ana_pll->sys_pll1_cfg1; in sscg_pll_init()
717 pll_cfg1 = &ana_pll->sys_pll2_cfg1; in sscg_pll_init()
732 pll_cfg1 = &ana_pll->sys_pll3_cfg1; in sscg_pll_init()
749 writel(val_cfg1, pll_cfg1); in sscg_pll_init()
[all …]
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/arch/arm/mach-imx/imx8m/
H A Dclock.c20 u32 pll_cfg0, pll_cfg1, pllout; in decode_frac_pll() local
28 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); in decode_frac_pll()
80 u32 pll_cfg0, pll_cfg1, pll_cfg2; in decode_sscg_pll() local
234 sse = pll_cfg1 & SSCG_PLL_SSE_MASK; in decode_sscg_pll()
660 pll_cfg1 = &ana_pll->arm_pll_cfg1; in frac_pll_init()
678 writel(val_cfg1, pll_cfg1); in frac_pll_init()
702 pll_cfg1 = &ana_pll->sys_pll1_cfg1; in sscg_pll_init()
717 pll_cfg1 = &ana_pll->sys_pll2_cfg1; in sscg_pll_init()
732 pll_cfg1 = &ana_pll->sys_pll3_cfg1; in sscg_pll_init()
749 writel(val_cfg1, pll_cfg1); in sscg_pll_init()
[all …]
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mq.c24 u32 pll_cfg0, pll_cfg1, pllout; in decode_frac_pll() local
32 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); in decode_frac_pll()
72 divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK; in decode_frac_pll()
84 u32 pll_cfg0, pll_cfg1, pll_cfg2; in decode_sscg_pll() local
103 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1); in decode_sscg_pll()
118 pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1); in decode_sscg_pll()
125 pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1); in decode_sscg_pll()
132 pll_cfg1 = readl(&ana_pll->dram_pll_cfg1); in decode_sscg_pll()
238 sse = pll_cfg1 & SSCG_PLL_SSE_MASK; in decode_sscg_pll()
672 pll_cfg1 = &ana_pll->arm_pll_cfg1; in frac_pll_init()
[all …]
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mq.c24 u32 pll_cfg0, pll_cfg1, pllout; in decode_frac_pll() local
32 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); in decode_frac_pll()
72 divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK; in decode_frac_pll()
84 u32 pll_cfg0, pll_cfg1, pll_cfg2; in decode_sscg_pll() local
103 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1); in decode_sscg_pll()
118 pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1); in decode_sscg_pll()
125 pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1); in decode_sscg_pll()
132 pll_cfg1 = readl(&ana_pll->dram_pll_cfg1); in decode_sscg_pll()
238 sse = pll_cfg1 & SSCG_PLL_SSE_MASK; in decode_sscg_pll()
672 pll_cfg1 = &ana_pll->arm_pll_cfg1; in frac_pll_init()
[all …]
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mq.c24 u32 pll_cfg0, pll_cfg1, pllout; in decode_frac_pll() local
32 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); in decode_frac_pll()
72 divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK; in decode_frac_pll()
84 u32 pll_cfg0, pll_cfg1, pll_cfg2; in decode_sscg_pll() local
103 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1); in decode_sscg_pll()
118 pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1); in decode_sscg_pll()
125 pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1); in decode_sscg_pll()
132 pll_cfg1 = readl(&ana_pll->dram_pll_cfg1); in decode_sscg_pll()
238 sse = pll_cfg1 & SSCG_PLL_SSE_MASK; in decode_sscg_pll()
672 pll_cfg1 = &ana_pll->arm_pll_cfg1; in frac_pll_init()
[all …]
/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mq.c24 u32 pll_cfg0, pll_cfg1, pllout; in decode_frac_pll() local
32 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); in decode_frac_pll()
72 divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK; in decode_frac_pll()
84 u32 pll_cfg0, pll_cfg1, pll_cfg2; in decode_sscg_pll() local
103 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1); in decode_sscg_pll()
118 pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1); in decode_sscg_pll()
125 pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1); in decode_sscg_pll()
132 pll_cfg1 = readl(&ana_pll->dram_pll_cfg1); in decode_sscg_pll()
238 sse = pll_cfg1 & SSCG_PLL_SSE_MASK; in decode_sscg_pll()
672 pll_cfg1 = &ana_pll->arm_pll_cfg1; in frac_pll_init()
[all …]
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mq.c24 u32 pll_cfg0, pll_cfg1, pllout; in decode_frac_pll() local
32 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); in decode_frac_pll()
72 divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK; in decode_frac_pll()
84 u32 pll_cfg0, pll_cfg1, pll_cfg2; in decode_sscg_pll() local
103 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1); in decode_sscg_pll()
118 pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1); in decode_sscg_pll()
125 pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1); in decode_sscg_pll()
132 pll_cfg1 = readl(&ana_pll->dram_pll_cfg1); in decode_sscg_pll()
238 sse = pll_cfg1 & SSCG_PLL_SSE_MASK; in decode_sscg_pll()
672 pll_cfg1 = &ana_pll->arm_pll_cfg1; in frac_pll_init()
[all …]
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mq.c24 u32 pll_cfg0, pll_cfg1, pllout; in decode_frac_pll() local
32 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); in decode_frac_pll()
72 divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK; in decode_frac_pll()
84 u32 pll_cfg0, pll_cfg1, pll_cfg2; in decode_sscg_pll() local
103 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1); in decode_sscg_pll()
118 pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1); in decode_sscg_pll()
125 pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1); in decode_sscg_pll()
132 pll_cfg1 = readl(&ana_pll->dram_pll_cfg1); in decode_sscg_pll()
238 sse = pll_cfg1 & SSCG_PLL_SSE_MASK; in decode_sscg_pll()
672 pll_cfg1 = &ana_pll->arm_pll_cfg1; in frac_pll_init()
[all …]
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mq.c24 u32 pll_cfg0, pll_cfg1, pllout; in decode_frac_pll() local
32 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); in decode_frac_pll()
72 divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK; in decode_frac_pll()
84 u32 pll_cfg0, pll_cfg1, pll_cfg2; in decode_sscg_pll() local
103 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1); in decode_sscg_pll()
118 pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1); in decode_sscg_pll()
125 pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1); in decode_sscg_pll()
132 pll_cfg1 = readl(&ana_pll->dram_pll_cfg1); in decode_sscg_pll()
238 sse = pll_cfg1 & SSCG_PLL_SSE_MASK; in decode_sscg_pll()
672 pll_cfg1 = &ana_pll->arm_pll_cfg1; in frac_pll_init()
[all …]
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mq.c24 u32 pll_cfg0, pll_cfg1, pllout; in decode_frac_pll() local
32 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); in decode_frac_pll()
72 divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK; in decode_frac_pll()
84 u32 pll_cfg0, pll_cfg1, pll_cfg2; in decode_sscg_pll() local
103 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1); in decode_sscg_pll()
118 pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1); in decode_sscg_pll()
125 pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1); in decode_sscg_pll()
132 pll_cfg1 = readl(&ana_pll->dram_pll_cfg1); in decode_sscg_pll()
238 sse = pll_cfg1 & SSCG_PLL_SSE_MASK; in decode_sscg_pll()
672 pll_cfg1 = &ana_pll->arm_pll_cfg1; in frac_pll_init()
[all …]
/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mq.c24 u32 pll_cfg0, pll_cfg1, pllout; in decode_frac_pll() local
32 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); in decode_frac_pll()
72 divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK; in decode_frac_pll()
84 u32 pll_cfg0, pll_cfg1, pll_cfg2; in decode_sscg_pll() local
103 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1); in decode_sscg_pll()
118 pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1); in decode_sscg_pll()
125 pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1); in decode_sscg_pll()
132 pll_cfg1 = readl(&ana_pll->dram_pll_cfg1); in decode_sscg_pll()
238 sse = pll_cfg1 & SSCG_PLL_SSE_MASK; in decode_sscg_pll()
672 pll_cfg1 = &ana_pll->arm_pll_cfg1; in frac_pll_init()
[all …]
/dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mq.c24 u32 pll_cfg0, pll_cfg1, pllout; in decode_frac_pll() local
32 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); in decode_frac_pll()
72 divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK; in decode_frac_pll()
84 u32 pll_cfg0, pll_cfg1, pll_cfg2; in decode_sscg_pll() local
103 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1); in decode_sscg_pll()
118 pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1); in decode_sscg_pll()
125 pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1); in decode_sscg_pll()
132 pll_cfg1 = readl(&ana_pll->dram_pll_cfg1); in decode_sscg_pll()
238 sse = pll_cfg1 & SSCG_PLL_SSE_MASK; in decode_sscg_pll()
672 pll_cfg1 = &ana_pll->arm_pll_cfg1; in frac_pll_init()
[all …]
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mq.c24 u32 pll_cfg0, pll_cfg1, pllout; in decode_frac_pll() local
32 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); in decode_frac_pll()
72 divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK; in decode_frac_pll()
84 u32 pll_cfg0, pll_cfg1, pll_cfg2; in decode_sscg_pll() local
103 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1); in decode_sscg_pll()
118 pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1); in decode_sscg_pll()
125 pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1); in decode_sscg_pll()
132 pll_cfg1 = readl(&ana_pll->dram_pll_cfg1); in decode_sscg_pll()
238 sse = pll_cfg1 & SSCG_PLL_SSE_MASK; in decode_sscg_pll()
672 pll_cfg1 = &ana_pll->arm_pll_cfg1; in frac_pll_init()
[all …]
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mq.c24 u32 pll_cfg0, pll_cfg1, pllout; in decode_frac_pll() local
32 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); in decode_frac_pll()
72 divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK; in decode_frac_pll()
84 u32 pll_cfg0, pll_cfg1, pll_cfg2; in decode_sscg_pll() local
103 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1); in decode_sscg_pll()
118 pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1); in decode_sscg_pll()
125 pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1); in decode_sscg_pll()
132 pll_cfg1 = readl(&ana_pll->dram_pll_cfg1); in decode_sscg_pll()
238 sse = pll_cfg1 & SSCG_PLL_SSE_MASK; in decode_sscg_pll()
672 pll_cfg1 = &ana_pll->arm_pll_cfg1; in frac_pll_init()
[all …]
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mq.c24 u32 pll_cfg0, pll_cfg1, pllout; in decode_frac_pll() local
32 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); in decode_frac_pll()
72 divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK; in decode_frac_pll()
84 u32 pll_cfg0, pll_cfg1, pll_cfg2; in decode_sscg_pll() local
103 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1); in decode_sscg_pll()
118 pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1); in decode_sscg_pll()
125 pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1); in decode_sscg_pll()
132 pll_cfg1 = readl(&ana_pll->dram_pll_cfg1); in decode_sscg_pll()
238 sse = pll_cfg1 & SSCG_PLL_SSE_MASK; in decode_sscg_pll()
672 pll_cfg1 = &ana_pll->arm_pll_cfg1; in frac_pll_init()
[all …]
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mq.c24 u32 pll_cfg0, pll_cfg1, pllout; in decode_frac_pll() local
32 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); in decode_frac_pll()
72 divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK; in decode_frac_pll()
84 u32 pll_cfg0, pll_cfg1, pll_cfg2; in decode_sscg_pll() local
103 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1); in decode_sscg_pll()
118 pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1); in decode_sscg_pll()
125 pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1); in decode_sscg_pll()
132 pll_cfg1 = readl(&ana_pll->dram_pll_cfg1); in decode_sscg_pll()
238 sse = pll_cfg1 & SSCG_PLL_SSE_MASK; in decode_sscg_pll()
672 pll_cfg1 = &ana_pll->arm_pll_cfg1; in frac_pll_init()
[all …]
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mq.c24 u32 pll_cfg0, pll_cfg1, pllout; in decode_frac_pll() local
32 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); in decode_frac_pll()
72 divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK; in decode_frac_pll()
84 u32 pll_cfg0, pll_cfg1, pll_cfg2; in decode_sscg_pll() local
103 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1); in decode_sscg_pll()
118 pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1); in decode_sscg_pll()
125 pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1); in decode_sscg_pll()
132 pll_cfg1 = readl(&ana_pll->dram_pll_cfg1); in decode_sscg_pll()
238 sse = pll_cfg1 & SSCG_PLL_SSE_MASK; in decode_sscg_pll()
672 pll_cfg1 = &ana_pll->arm_pll_cfg1; in frac_pll_init()
[all …]
/dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mq.c24 u32 pll_cfg0, pll_cfg1, pllout; in decode_frac_pll() local
32 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); in decode_frac_pll()
72 divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK; in decode_frac_pll()
84 u32 pll_cfg0, pll_cfg1, pll_cfg2; in decode_sscg_pll() local
103 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1); in decode_sscg_pll()
118 pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1); in decode_sscg_pll()
125 pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1); in decode_sscg_pll()
132 pll_cfg1 = readl(&ana_pll->dram_pll_cfg1); in decode_sscg_pll()
238 sse = pll_cfg1 & SSCG_PLL_SSE_MASK; in decode_sscg_pll()
672 pll_cfg1 = &ana_pll->arm_pll_cfg1; in frac_pll_init()
[all …]
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mq.c24 u32 pll_cfg0, pll_cfg1, pllout; in decode_frac_pll() local
32 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); in decode_frac_pll()
72 divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK; in decode_frac_pll()
84 u32 pll_cfg0, pll_cfg1, pll_cfg2; in decode_sscg_pll() local
103 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1); in decode_sscg_pll()
118 pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1); in decode_sscg_pll()
125 pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1); in decode_sscg_pll()
132 pll_cfg1 = readl(&ana_pll->dram_pll_cfg1); in decode_sscg_pll()
238 sse = pll_cfg1 & SSCG_PLL_SSE_MASK; in decode_sscg_pll()
672 pll_cfg1 = &ana_pll->arm_pll_cfg1; in frac_pll_init()
[all …]
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mq.c24 u32 pll_cfg0, pll_cfg1, pllout; in decode_frac_pll() local
32 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); in decode_frac_pll()
72 divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK; in decode_frac_pll()
84 u32 pll_cfg0, pll_cfg1, pll_cfg2; in decode_sscg_pll() local
103 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1); in decode_sscg_pll()
118 pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1); in decode_sscg_pll()
125 pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1); in decode_sscg_pll()
132 pll_cfg1 = readl(&ana_pll->dram_pll_cfg1); in decode_sscg_pll()
238 sse = pll_cfg1 & SSCG_PLL_SSE_MASK; in decode_sscg_pll()
672 pll_cfg1 = &ana_pll->arm_pll_cfg1; in frac_pll_init()
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/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mq.c24 u32 pll_cfg0, pll_cfg1, pllout; in decode_frac_pll() local
32 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); in decode_frac_pll()
72 divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK; in decode_frac_pll()
84 u32 pll_cfg0, pll_cfg1, pll_cfg2; in decode_sscg_pll() local
103 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1); in decode_sscg_pll()
118 pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1); in decode_sscg_pll()
125 pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1); in decode_sscg_pll()
132 pll_cfg1 = readl(&ana_pll->dram_pll_cfg1); in decode_sscg_pll()
238 sse = pll_cfg1 & SSCG_PLL_SSE_MASK; in decode_sscg_pll()
672 pll_cfg1 = &ana_pll->arm_pll_cfg1; in frac_pll_init()
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/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/mach-imx/imx8m/
H A Dclock_imx8mq.c24 u32 pll_cfg0, pll_cfg1, pllout; in decode_frac_pll() local
32 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); in decode_frac_pll()
72 divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK; in decode_frac_pll()
84 u32 pll_cfg0, pll_cfg1, pll_cfg2; in decode_sscg_pll() local
103 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1); in decode_sscg_pll()
118 pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1); in decode_sscg_pll()
125 pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1); in decode_sscg_pll()
132 pll_cfg1 = readl(&ana_pll->dram_pll_cfg1); in decode_sscg_pll()
238 sse = pll_cfg1 & SSCG_PLL_SSE_MASK; in decode_sscg_pll()
672 pll_cfg1 = &ana_pll->arm_pll_cfg1; in frac_pll_init()
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