| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 45 unsigned long pllcr; in get_clocks() local
52 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ in get_clocks()
54 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ in get_clocks()
59 pllcr = CONFIG_SYS_PLLCR; in get_clocks()
64 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ in get_clocks()
65 pllcr ^= 0x00000001; /* Set pll bypass to 1 */ in get_clocks()
66 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ in get_clocks()
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 45 unsigned long pllcr; in get_clocks() local
52 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ in get_clocks()
54 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ in get_clocks()
59 pllcr = CONFIG_SYS_PLLCR; in get_clocks()
64 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ in get_clocks()
65 pllcr ^= 0x00000001; /* Set pll bypass to 1 */ in get_clocks()
66 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ in get_clocks()
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 45 unsigned long pllcr; in get_clocks() local
52 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ in get_clocks()
54 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ in get_clocks()
59 pllcr = CONFIG_SYS_PLLCR; in get_clocks()
64 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ in get_clocks()
65 pllcr ^= 0x00000001; /* Set pll bypass to 1 */ in get_clocks()
66 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ in get_clocks()
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 45 unsigned long pllcr; in get_clocks() local
52 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ in get_clocks()
54 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ in get_clocks()
59 pllcr = CONFIG_SYS_PLLCR; in get_clocks()
64 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ in get_clocks()
65 pllcr ^= 0x00000001; /* Set pll bypass to 1 */ in get_clocks()
66 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ in get_clocks()
|
| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 45 unsigned long pllcr; in get_clocks() local
52 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ in get_clocks()
54 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ in get_clocks()
59 pllcr = CONFIG_SYS_PLLCR; in get_clocks()
64 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ in get_clocks()
65 pllcr ^= 0x00000001; /* Set pll bypass to 1 */ in get_clocks()
66 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ in get_clocks()
|
| /dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 45 unsigned long pllcr; in get_clocks() local
52 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ in get_clocks()
54 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ in get_clocks()
59 pllcr = CONFIG_SYS_PLLCR; in get_clocks()
64 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ in get_clocks()
65 pllcr ^= 0x00000001; /* Set pll bypass to 1 */ in get_clocks()
66 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ in get_clocks()
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 45 unsigned long pllcr; in get_clocks() local
52 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ in get_clocks()
54 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ in get_clocks()
59 pllcr = CONFIG_SYS_PLLCR; in get_clocks()
64 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ in get_clocks()
65 pllcr ^= 0x00000001; /* Set pll bypass to 1 */ in get_clocks()
66 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ in get_clocks()
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 29 unsigned long pllcr; in get_clocks() local
36 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ in get_clocks()
38 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ in get_clocks()
43 pllcr = CONFIG_SYS_PLLCR; in get_clocks()
48 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ in get_clocks()
49 pllcr ^= 0x00000001; /* Set pll bypass to 1 */ in get_clocks()
50 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ in get_clocks()
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 29 unsigned long pllcr; in get_clocks() local
36 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ in get_clocks()
38 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ in get_clocks()
43 pllcr = CONFIG_SYS_PLLCR; in get_clocks()
48 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ in get_clocks()
49 pllcr ^= 0x00000001; /* Set pll bypass to 1 */ in get_clocks()
50 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ in get_clocks()
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 32 unsigned long pllcr; in get_clocks() local
39 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ in get_clocks()
41 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ in get_clocks()
46 pllcr = CONFIG_SYS_PLLCR; in get_clocks()
51 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ in get_clocks()
52 pllcr ^= 0x00000001; /* Set pll bypass to 1 */ in get_clocks()
53 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ in get_clocks()
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 32 unsigned long pllcr; in get_clocks() local
39 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ in get_clocks()
41 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ in get_clocks()
46 pllcr = CONFIG_SYS_PLLCR; in get_clocks()
51 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ in get_clocks()
52 pllcr ^= 0x00000001; /* Set pll bypass to 1 */ in get_clocks()
53 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ in get_clocks()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 32 unsigned long pllcr; in get_clocks() local
39 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ in get_clocks()
41 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ in get_clocks()
46 pllcr = CONFIG_SYS_PLLCR; in get_clocks()
51 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ in get_clocks()
52 pllcr ^= 0x00000001; /* Set pll bypass to 1 */ in get_clocks()
53 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ in get_clocks()
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 32 unsigned long pllcr; in get_clocks() local
39 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ in get_clocks()
41 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ in get_clocks()
46 pllcr = CONFIG_SYS_PLLCR; in get_clocks()
51 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ in get_clocks()
52 pllcr ^= 0x00000001; /* Set pll bypass to 1 */ in get_clocks()
53 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ in get_clocks()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 32 unsigned long pllcr; in get_clocks() local
39 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ in get_clocks()
41 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ in get_clocks()
46 pllcr = CONFIG_SYS_PLLCR; in get_clocks()
51 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ in get_clocks()
52 pllcr ^= 0x00000001; /* Set pll bypass to 1 */ in get_clocks()
53 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ in get_clocks()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 32 unsigned long pllcr; in get_clocks() local
39 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ in get_clocks()
41 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ in get_clocks()
46 pllcr = CONFIG_SYS_PLLCR; in get_clocks()
51 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ in get_clocks()
52 pllcr ^= 0x00000001; /* Set pll bypass to 1 */ in get_clocks()
53 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ in get_clocks()
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 32 unsigned long pllcr; in get_clocks() local
39 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ in get_clocks()
41 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ in get_clocks()
46 pllcr = CONFIG_SYS_PLLCR; in get_clocks()
51 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ in get_clocks()
52 pllcr ^= 0x00000001; /* Set pll bypass to 1 */ in get_clocks()
53 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ in get_clocks()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 32 unsigned long pllcr; in get_clocks() local
39 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ in get_clocks()
41 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ in get_clocks()
46 pllcr = CONFIG_SYS_PLLCR; in get_clocks()
51 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ in get_clocks()
52 pllcr ^= 0x00000001; /* Set pll bypass to 1 */ in get_clocks()
53 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ in get_clocks()
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 32 unsigned long pllcr; in get_clocks() local
39 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ in get_clocks()
41 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ in get_clocks()
46 pllcr = CONFIG_SYS_PLLCR; in get_clocks()
51 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ in get_clocks()
52 pllcr ^= 0x00000001; /* Set pll bypass to 1 */ in get_clocks()
53 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ in get_clocks()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 32 unsigned long pllcr; in get_clocks() local
39 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ in get_clocks()
41 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ in get_clocks()
46 pllcr = CONFIG_SYS_PLLCR; in get_clocks()
51 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ in get_clocks()
52 pllcr ^= 0x00000001; /* Set pll bypass to 1 */ in get_clocks()
53 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ in get_clocks()
|
| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 32 unsigned long pllcr; in get_clocks() local
39 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ in get_clocks()
41 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ in get_clocks()
46 pllcr = CONFIG_SYS_PLLCR; in get_clocks()
51 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ in get_clocks()
52 pllcr ^= 0x00000001; /* Set pll bypass to 1 */ in get_clocks()
53 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ in get_clocks()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 32 unsigned long pllcr; in get_clocks() local
39 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ in get_clocks()
41 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ in get_clocks()
46 pllcr = CONFIG_SYS_PLLCR; in get_clocks()
51 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ in get_clocks()
52 pllcr ^= 0x00000001; /* Set pll bypass to 1 */ in get_clocks()
53 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ in get_clocks()
|
| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 32 unsigned long pllcr; in get_clocks() local
39 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ in get_clocks()
41 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ in get_clocks()
46 pllcr = CONFIG_SYS_PLLCR; in get_clocks()
51 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ in get_clocks()
52 pllcr ^= 0x00000001; /* Set pll bypass to 1 */ in get_clocks()
53 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ in get_clocks()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 32 unsigned long pllcr; in get_clocks() local
39 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ in get_clocks()
41 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ in get_clocks()
46 pllcr = CONFIG_SYS_PLLCR; in get_clocks()
51 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ in get_clocks()
52 pllcr ^= 0x00000001; /* Set pll bypass to 1 */ in get_clocks()
53 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ in get_clocks()
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 32 unsigned long pllcr; in get_clocks() local
39 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ in get_clocks()
41 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ in get_clocks()
46 pllcr = CONFIG_SYS_PLLCR; in get_clocks()
51 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ in get_clocks()
52 pllcr ^= 0x00000001; /* Set pll bypass to 1 */ in get_clocks()
53 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ in get_clocks()
|
| /dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 32 unsigned long pllcr; in get_clocks() local
39 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ in get_clocks()
41 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ in get_clocks()
46 pllcr = CONFIG_SYS_PLLCR; in get_clocks()
51 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ in get_clocks()
52 pllcr ^= 0x00000001; /* Set pll bypass to 1 */ in get_clocks()
53 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ in get_clocks()
|