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Searched refs:pm_io_base (Results 1 – 25 of 50) sorted by relevance

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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/i2c/busses/
H A Di2c-via.c22 #define I2C_DIR (pm_io_base+0x40)
23 #define I2C_OUT (pm_io_base+0x42)
24 #define I2C_IN (pm_io_base+0x44)
32 static u16 pm_io_base; variable
92 if (pm_io_base) { in vt586b_probe()
113 pci_read_config_word(dev, base, &pm_io_base); in vt586b_probe()
114 pm_io_base &= (0xff << 8); in vt586b_probe()
130 pm_io_base = 0; in vt586b_probe()
140 pm_io_base = 0; in vt586b_remove()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/i2c/busses/
H A Di2c-via.c22 #define I2C_DIR (pm_io_base+0x40)
23 #define I2C_OUT (pm_io_base+0x42)
24 #define I2C_IN (pm_io_base+0x44)
32 static u16 pm_io_base; variable
92 if (pm_io_base) { in vt586b_probe()
113 pci_read_config_word(dev, base, &pm_io_base); in vt586b_probe()
114 pm_io_base &= (0xff << 8); in vt586b_probe()
130 pm_io_base = 0; in vt586b_probe()
140 pm_io_base = 0; in vt586b_remove()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/i2c/busses/
H A Di2c-via.c22 #define I2C_DIR (pm_io_base+0x40)
23 #define I2C_OUT (pm_io_base+0x42)
24 #define I2C_IN (pm_io_base+0x44)
32 static u16 pm_io_base; variable
92 if (pm_io_base) { in vt586b_probe()
113 pci_read_config_word(dev, base, &pm_io_base); in vt586b_probe()
114 pm_io_base &= (0xff << 8); in vt586b_probe()
130 pm_io_base = 0; in vt586b_probe()
140 pm_io_base = 0; in vt586b_remove()
/dports/emulators/qemu60/qemu-6.0.0/hw/acpi/
H A Dich9.c124 void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base) in ich9_pm_iospace_update() argument
126 ICH9_DEBUG("to 0x%x\n", pm_io_base); in ich9_pm_iospace_update()
128 assert((pm_io_base & ICH9_PMIO_MASK) == 0); in ich9_pm_iospace_update()
130 pm->pm_io_base = pm_io_base; in ich9_pm_iospace_update()
132 memory_region_set_enabled(&pm->io, pm->pm_io_base != 0); in ich9_pm_iospace_update()
133 memory_region_set_address(&pm->io, pm->pm_io_base); in ich9_pm_iospace_update()
140 uint32_t pm_io_base = pm->pm_io_base; in ich9_pm_post_load() local
141 pm->pm_io_base = 0; in ich9_pm_post_load()
142 ich9_pm_iospace_update(pm, pm_io_base); in ich9_pm_post_load()
320 uint32_t value = pm->pm_io_base + ICH9_PMIO_GPE0_STS; in ich9_pm_get_gpe0_blk()
[all …]
/dports/emulators/qemu5/qemu-5.2.0/hw/acpi/
H A Dich9.c124 void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base) in ich9_pm_iospace_update() argument
126 ICH9_DEBUG("to 0x%x\n", pm_io_base); in ich9_pm_iospace_update()
128 assert((pm_io_base & ICH9_PMIO_MASK) == 0); in ich9_pm_iospace_update()
130 pm->pm_io_base = pm_io_base; in ich9_pm_iospace_update()
132 memory_region_set_enabled(&pm->io, pm->pm_io_base != 0); in ich9_pm_iospace_update()
133 memory_region_set_address(&pm->io, pm->pm_io_base); in ich9_pm_iospace_update()
140 uint32_t pm_io_base = pm->pm_io_base; in ich9_pm_post_load() local
141 pm->pm_io_base = 0; in ich9_pm_post_load()
142 ich9_pm_iospace_update(pm, pm_io_base); in ich9_pm_post_load()
320 uint32_t value = pm->pm_io_base + ICH9_PMIO_GPE0_STS; in ich9_pm_get_gpe0_blk()
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/acpi/
H A Dich9.c124 void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base)
126 ICH9_DEBUG("to 0x%x\n", pm_io_base);
128 assert((pm_io_base & ICH9_PMIO_MASK) == 0);
130 pm->pm_io_base = pm_io_base;
132 memory_region_set_enabled(&pm->io, pm->pm_io_base != 0);
133 memory_region_set_address(&pm->io, pm->pm_io_base);
140 uint32_t pm_io_base = pm->pm_io_base;
141 pm->pm_io_base = 0;
142 ich9_pm_iospace_update(pm, pm_io_base);
320 uint32_t value = pm->pm_io_base + ICH9_PMIO_GPE0_STS;
[all …]
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/acpi/
H A Dich9.c124 void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base) in ich9_pm_iospace_update() argument
126 ICH9_DEBUG("to 0x%x\n", pm_io_base); in ich9_pm_iospace_update()
128 assert((pm_io_base & ICH9_PMIO_MASK) == 0); in ich9_pm_iospace_update()
130 pm->pm_io_base = pm_io_base; in ich9_pm_iospace_update()
132 memory_region_set_enabled(&pm->io, pm->pm_io_base != 0); in ich9_pm_iospace_update()
133 memory_region_set_address(&pm->io, pm->pm_io_base); in ich9_pm_iospace_update()
140 uint32_t pm_io_base = pm->pm_io_base; in ich9_pm_post_load() local
141 pm->pm_io_base = 0; in ich9_pm_post_load()
142 ich9_pm_iospace_update(pm, pm_io_base); in ich9_pm_post_load()
320 uint32_t value = pm->pm_io_base + ICH9_PMIO_GPE0_STS; in ich9_pm_get_gpe0_blk()
[all …]
/dports/emulators/qemu42/qemu-4.2.1/hw/acpi/
H A Dich9.c124 void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base) in ich9_pm_iospace_update() argument
126 ICH9_DEBUG("to 0x%x\n", pm_io_base); in ich9_pm_iospace_update()
128 assert((pm_io_base & ICH9_PMIO_MASK) == 0); in ich9_pm_iospace_update()
130 pm->pm_io_base = pm_io_base; in ich9_pm_iospace_update()
132 memory_region_set_enabled(&pm->io, pm->pm_io_base != 0); in ich9_pm_iospace_update()
133 memory_region_set_address(&pm->io, pm->pm_io_base); in ich9_pm_iospace_update()
140 uint32_t pm_io_base = pm->pm_io_base; in ich9_pm_post_load() local
141 pm->pm_io_base = 0; in ich9_pm_post_load()
142 ich9_pm_iospace_update(pm, pm_io_base); in ich9_pm_post_load()
320 uint32_t value = pm->pm_io_base + ICH9_PMIO_GPE0_STS; in ich9_pm_get_gpe0_blk()
[all …]
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/acpi/
H A Dich9.c121 void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base) in ich9_pm_iospace_update() argument
123 ICH9_DEBUG("to 0x%x\n", pm_io_base); in ich9_pm_iospace_update()
125 assert((pm_io_base & ICH9_PMIO_MASK) == 0); in ich9_pm_iospace_update()
127 pm->pm_io_base = pm_io_base; in ich9_pm_iospace_update()
129 memory_region_set_enabled(&pm->io, pm->pm_io_base != 0); in ich9_pm_iospace_update()
130 memory_region_set_address(&pm->io, pm->pm_io_base); in ich9_pm_iospace_update()
137 uint32_t pm_io_base = pm->pm_io_base; in ich9_pm_post_load() local
138 pm->pm_io_base = 0; in ich9_pm_post_load()
139 ich9_pm_iospace_update(pm, pm_io_base); in ich9_pm_post_load()
317 uint32_t value = pm->pm_io_base + ICH9_PMIO_GPE0_STS; in ich9_pm_get_gpe0_blk()
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/hw/acpi/
H A Dich9.c124 void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base) in ich9_pm_iospace_update() argument
126 ICH9_DEBUG("to 0x%x\n", pm_io_base); in ich9_pm_iospace_update()
128 assert((pm_io_base & ICH9_PMIO_MASK) == 0); in ich9_pm_iospace_update()
130 pm->pm_io_base = pm_io_base; in ich9_pm_iospace_update()
132 memory_region_set_enabled(&pm->io, pm->pm_io_base != 0); in ich9_pm_iospace_update()
133 memory_region_set_address(&pm->io, pm->pm_io_base); in ich9_pm_iospace_update()
140 uint32_t pm_io_base = pm->pm_io_base; in ich9_pm_post_load() local
141 pm->pm_io_base = 0; in ich9_pm_post_load()
142 ich9_pm_iospace_update(pm, pm_io_base); in ich9_pm_post_load()
320 uint32_t value = pm->pm_io_base + ICH9_PMIO_GPE0_STS; in ich9_pm_get_gpe0_blk()
[all …]
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/acpi/
H A Dich9.c123 void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base) in ich9_pm_iospace_update() argument
125 ICH9_DEBUG("to 0x%x\n", pm_io_base); in ich9_pm_iospace_update()
127 assert((pm_io_base & ICH9_PMIO_MASK) == 0); in ich9_pm_iospace_update()
129 pm->pm_io_base = pm_io_base; in ich9_pm_iospace_update()
131 memory_region_set_enabled(&pm->io, pm->pm_io_base != 0); in ich9_pm_iospace_update()
132 memory_region_set_address(&pm->io, pm->pm_io_base); in ich9_pm_iospace_update()
139 uint32_t pm_io_base = pm->pm_io_base; in ich9_pm_post_load() local
140 pm->pm_io_base = 0; in ich9_pm_post_load()
141 ich9_pm_iospace_update(pm, pm_io_base); in ich9_pm_post_load()
356 uint32_t value = pm->pm_io_base + ICH9_PMIO_GPE0_STS; in ich9_pm_get_gpe0_blk()
[all …]
/dports/emulators/qemu/qemu-6.2.0/hw/acpi/
H A Dich9.c123 void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base) in ich9_pm_iospace_update() argument
125 ICH9_DEBUG("to 0x%x\n", pm_io_base); in ich9_pm_iospace_update()
127 assert((pm_io_base & ICH9_PMIO_MASK) == 0); in ich9_pm_iospace_update()
129 pm->pm_io_base = pm_io_base; in ich9_pm_iospace_update()
131 memory_region_set_enabled(&pm->io, pm->pm_io_base != 0); in ich9_pm_iospace_update()
132 memory_region_set_address(&pm->io, pm->pm_io_base); in ich9_pm_iospace_update()
139 uint32_t pm_io_base = pm->pm_io_base; in ich9_pm_post_load() local
140 pm->pm_io_base = 0; in ich9_pm_post_load()
141 ich9_pm_iospace_update(pm, pm_io_base); in ich9_pm_post_load()
356 uint32_t value = pm->pm_io_base + ICH9_PMIO_GPE0_STS; in ich9_pm_get_gpe0_blk()
[all …]
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/include/hw/acpi/
H A Dich9.h49 uint32_t pm_io_base; member
72 void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base);
/dports/emulators/qemu42/qemu-4.2.1/include/hw/acpi/
H A Dich9.h49 uint32_t pm_io_base; member
72 void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base);
/dports/emulators/qemu/qemu-6.2.0/include/hw/acpi/
H A Dich9.h52 uint32_t pm_io_base; member
79 void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base);
/dports/emulators/qemu60/qemu-6.0.0/include/hw/acpi/
H A Dich9.h49 uint32_t pm_io_base; member
73 void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base);
/dports/emulators/qemu-utils/qemu-4.2.1/include/hw/acpi/
H A Dich9.h49 uint32_t pm_io_base; member
72 void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base);
/dports/emulators/qemu5/qemu-5.2.0/include/hw/acpi/
H A Dich9.h49 uint32_t pm_io_base; member
72 void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base);
/dports/emulators/qemu-guest-agent/qemu-5.0.1/include/hw/acpi/
H A Dich9.h49 uint32_t pm_io_base;
72 void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base);
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/include/hw/acpi/
H A Dich9.h52 uint32_t pm_io_base; member
78 void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base);
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/include/hw/acpi/
H A Dich9.h49 uint32_t pm_io_base; member
72 void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base);
/dports/emulators/qemu42/qemu-4.2.1/hw/isa/
H A Dvt82c686.c215 uint32_t pm_io_base; in pm_io_space_update() local
217 pm_io_base = pci_get_long(s->dev.config + 0x40); in pm_io_space_update()
218 pm_io_base &= 0xffc0; in pm_io_space_update()
222 memory_region_set_address(&s->io, pm_io_base); in pm_io_space_update()
/dports/emulators/qemu-utils/qemu-4.2.1/hw/isa/
H A Dvt82c686.c215 uint32_t pm_io_base; in pm_io_space_update() local
217 pm_io_base = pci_get_long(s->dev.config + 0x40); in pm_io_space_update()
218 pm_io_base &= 0xffc0; in pm_io_space_update()
222 memory_region_set_address(&s->io, pm_io_base); in pm_io_space_update()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/isa/
H A Dvt82c686.c216 uint32_t pm_io_base; in pm_io_space_update() local
218 pm_io_base = pci_get_long(s->dev.config + 0x40); in pm_io_space_update()
219 pm_io_base &= 0xffc0; in pm_io_space_update()
223 memory_region_set_address(&s->io, pm_io_base); in pm_io_space_update()
/dports/emulators/qemu5/qemu-5.2.0/hw/isa/
H A Dvt82c686.c212 uint32_t pm_io_base; in pm_io_space_update() local
214 pm_io_base = pci_get_long(s->dev.config + 0x40); in pm_io_space_update()
215 pm_io_base &= 0xffc0; in pm_io_space_update()
219 memory_region_set_address(&s->io, pm_io_base); in pm_io_space_update()

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