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Searched refs:pm_regs (Results 1 – 23 of 23) sorted by relevance

/dports/devel/openocd/openocd-0.11.0/src/target/
H A Dlakemont.c529 x86_32->pm_regs[I(EFLAGS)], in halt_prep()
530 x86_32->pm_regs[I(EFLAGS)] & EFLAGS_VM86 ? 1 : 0, in halt_prep()
531 x86_32->pm_regs[I(EFLAGS)] & EFLAGS_IF ? 1 : 0); in halt_prep()
536 x86_32->pm_regs[I(CSAR)] = csar & ~CSAR_DPL; in halt_prep()
542 x86_32->pm_regs[I(SSAR)] = ssar & ~SSAR_DPL; in halt_prep()
552 x86_32->pm_regs[I(CR0)] = cr0 & ~CR0_PG; in halt_prep()
559 x86_32->pm_regs[I(CR0)] = in halt_prep()
560 x86_32->pm_regs[I(CR0)] | (CR0_CD | CR0_NW | CR0_PG); in halt_prep()
721 if (x86_32->pm_regs[I(CR0)] & CR0_PG) in is_paging_enabled()
736 x86_32->pm_regs[I(CR0)] = x86_32->pm_regs[I(CR0)] & ~CR0_PG; in disable_paging()
[all …]
H A Dx86_32_common.h224 uint32_t pm_regs[NUM_PM_REGS]; member
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/tty/serial/
H A Dmvebu-uart.c134 struct mvebu_uart_pm_regs pm_regs; member
765 mvuart->pm_regs.rbr = readl(port->membase + UART_RBR(port)); in mvebu_uart_suspend()
766 mvuart->pm_regs.tsh = readl(port->membase + UART_TSH(port)); in mvebu_uart_suspend()
769 mvuart->pm_regs.stat = readl(port->membase + UART_STAT); in mvebu_uart_suspend()
770 mvuart->pm_regs.brdv = readl(port->membase + UART_BRDV); in mvebu_uart_suspend()
771 mvuart->pm_regs.osamp = readl(port->membase + UART_OSAMP); in mvebu_uart_suspend()
783 writel(mvuart->pm_regs.rbr, port->membase + UART_RBR(port)); in mvebu_uart_resume()
784 writel(mvuart->pm_regs.tsh, port->membase + UART_TSH(port)); in mvebu_uart_resume()
787 writel(mvuart->pm_regs.stat, port->membase + UART_STAT); in mvebu_uart_resume()
788 writel(mvuart->pm_regs.brdv, port->membase + UART_BRDV); in mvebu_uart_resume()
[all …]
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/tty/serial/
H A Dmvebu-uart.c134 struct mvebu_uart_pm_regs pm_regs; member
765 mvuart->pm_regs.rbr = readl(port->membase + UART_RBR(port)); in mvebu_uart_suspend()
766 mvuart->pm_regs.tsh = readl(port->membase + UART_TSH(port)); in mvebu_uart_suspend()
769 mvuart->pm_regs.stat = readl(port->membase + UART_STAT); in mvebu_uart_suspend()
770 mvuart->pm_regs.brdv = readl(port->membase + UART_BRDV); in mvebu_uart_suspend()
771 mvuart->pm_regs.osamp = readl(port->membase + UART_OSAMP); in mvebu_uart_suspend()
783 writel(mvuart->pm_regs.rbr, port->membase + UART_RBR(port)); in mvebu_uart_resume()
784 writel(mvuart->pm_regs.tsh, port->membase + UART_TSH(port)); in mvebu_uart_resume()
787 writel(mvuart->pm_regs.stat, port->membase + UART_STAT); in mvebu_uart_resume()
788 writel(mvuart->pm_regs.brdv, port->membase + UART_BRDV); in mvebu_uart_resume()
[all …]
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/tty/serial/
H A Dmvebu-uart.c134 struct mvebu_uart_pm_regs pm_regs; member
765 mvuart->pm_regs.rbr = readl(port->membase + UART_RBR(port)); in mvebu_uart_suspend()
766 mvuart->pm_regs.tsh = readl(port->membase + UART_TSH(port)); in mvebu_uart_suspend()
769 mvuart->pm_regs.stat = readl(port->membase + UART_STAT); in mvebu_uart_suspend()
770 mvuart->pm_regs.brdv = readl(port->membase + UART_BRDV); in mvebu_uart_suspend()
771 mvuart->pm_regs.osamp = readl(port->membase + UART_OSAMP); in mvebu_uart_suspend()
783 writel(mvuart->pm_regs.rbr, port->membase + UART_RBR(port)); in mvebu_uart_resume()
784 writel(mvuart->pm_regs.tsh, port->membase + UART_TSH(port)); in mvebu_uart_resume()
787 writel(mvuart->pm_regs.stat, port->membase + UART_STAT); in mvebu_uart_resume()
788 writel(mvuart->pm_regs.brdv, port->membase + UART_BRDV); in mvebu_uart_resume()
[all …]
/dports/emulators/qemu/qemu-6.2.0/hw/arm/
H A Dpxa2xx.c116 return s->pm_regs[addr >> 2]; in pxa2xx_pm_read()
135 s->pm_regs[addr >> 2] &= ~(value & 0x2a); in pxa2xx_pm_write()
137 s->pm_regs[addr >> 2] &= ~0x15; in pxa2xx_pm_write()
138 s->pm_regs[addr >> 2] |= value & 0x15; in pxa2xx_pm_write()
144 s->pm_regs[addr >> 2] &= ~value; in pxa2xx_pm_write()
149 s->pm_regs[addr >> 2] = value; in pxa2xx_pm_write()
291 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ in pxa2xx_pwrmode_write()
301 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ in pxa2xx_pwrmode_write()
302 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ in pxa2xx_pwrmode_write()
311 s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2]; in pxa2xx_pwrmode_write()
[all …]
/dports/emulators/qemu42/qemu-4.2.1/hw/arm/
H A Dpxa2xx.c112 return s->pm_regs[addr >> 2]; in pxa2xx_pm_read()
129 s->pm_regs[addr >> 2] &= ~(value & 0x2a); in pxa2xx_pm_write()
131 s->pm_regs[addr >> 2] &= ~0x15; in pxa2xx_pm_write()
132 s->pm_regs[addr >> 2] |= value & 0x15; in pxa2xx_pm_write()
138 s->pm_regs[addr >> 2] &= ~value; in pxa2xx_pm_write()
143 s->pm_regs[addr >> 2] = value; in pxa2xx_pm_write()
280 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ in pxa2xx_pwrmode_write()
290 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ in pxa2xx_pwrmode_write()
291 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ in pxa2xx_pwrmode_write()
300 s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2]; in pxa2xx_pwrmode_write()
[all …]
/dports/emulators/qemu60/qemu-6.0.0/hw/arm/
H A Dpxa2xx.c116 return s->pm_regs[addr >> 2]; in pxa2xx_pm_read()
135 s->pm_regs[addr >> 2] &= ~(value & 0x2a); in pxa2xx_pm_write()
137 s->pm_regs[addr >> 2] &= ~0x15; in pxa2xx_pm_write()
138 s->pm_regs[addr >> 2] |= value & 0x15; in pxa2xx_pm_write()
144 s->pm_regs[addr >> 2] &= ~value; in pxa2xx_pm_write()
149 s->pm_regs[addr >> 2] = value; in pxa2xx_pm_write()
291 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ in pxa2xx_pwrmode_write()
301 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ in pxa2xx_pwrmode_write()
302 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ in pxa2xx_pwrmode_write()
311 s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2]; in pxa2xx_pwrmode_write()
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/hw/arm/
H A Dpxa2xx.c112 return s->pm_regs[addr >> 2]; in pxa2xx_pm_read()
129 s->pm_regs[addr >> 2] &= ~(value & 0x2a); in pxa2xx_pm_write()
131 s->pm_regs[addr >> 2] &= ~0x15; in pxa2xx_pm_write()
132 s->pm_regs[addr >> 2] |= value & 0x15; in pxa2xx_pm_write()
138 s->pm_regs[addr >> 2] &= ~value; in pxa2xx_pm_write()
143 s->pm_regs[addr >> 2] = value; in pxa2xx_pm_write()
280 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ in pxa2xx_pwrmode_write()
290 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ in pxa2xx_pwrmode_write()
291 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ in pxa2xx_pwrmode_write()
300 s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2]; in pxa2xx_pwrmode_write()
[all …]
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/arm/
H A Dpxa2xx.c108 return s->pm_regs[addr >> 2]; in pxa2xx_pm_read()
125 s->pm_regs[addr >> 2] &= ~(value & 0x2a); in pxa2xx_pm_write()
127 s->pm_regs[addr >> 2] &= ~0x15; in pxa2xx_pm_write()
128 s->pm_regs[addr >> 2] |= value & 0x15; in pxa2xx_pm_write()
134 s->pm_regs[addr >> 2] &= ~value; in pxa2xx_pm_write()
139 s->pm_regs[addr >> 2] = value; in pxa2xx_pm_write()
276 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ in pxa2xx_pwrmode_write()
286 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ in pxa2xx_pwrmode_write()
287 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ in pxa2xx_pwrmode_write()
296 s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2]; in pxa2xx_pwrmode_write()
[all …]
/dports/emulators/qemu5/qemu-5.2.0/hw/arm/
H A Dpxa2xx.c115 return s->pm_regs[addr >> 2]; in pxa2xx_pm_read()
134 s->pm_regs[addr >> 2] &= ~(value & 0x2a); in pxa2xx_pm_write()
136 s->pm_regs[addr >> 2] &= ~0x15; in pxa2xx_pm_write()
137 s->pm_regs[addr >> 2] |= value & 0x15; in pxa2xx_pm_write()
143 s->pm_regs[addr >> 2] &= ~value; in pxa2xx_pm_write()
148 s->pm_regs[addr >> 2] = value; in pxa2xx_pm_write()
290 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ in pxa2xx_pwrmode_write()
300 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ in pxa2xx_pwrmode_write()
301 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ in pxa2xx_pwrmode_write()
310 s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2]; in pxa2xx_pwrmode_write()
[all …]
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/arm/
H A Dpxa2xx.c112 return s->pm_regs[addr >> 2]; in pxa2xx_pm_read()
129 s->pm_regs[addr >> 2] &= ~(value & 0x2a); in pxa2xx_pm_write()
131 s->pm_regs[addr >> 2] &= ~0x15; in pxa2xx_pm_write()
132 s->pm_regs[addr >> 2] |= value & 0x15; in pxa2xx_pm_write()
138 s->pm_regs[addr >> 2] &= ~value; in pxa2xx_pm_write()
143 s->pm_regs[addr >> 2] = value; in pxa2xx_pm_write()
280 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ in pxa2xx_pwrmode_write()
290 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ in pxa2xx_pwrmode_write()
291 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ in pxa2xx_pwrmode_write()
300 s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2]; in pxa2xx_pwrmode_write()
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/arm/
H A Dpxa2xx.c112 return s->pm_regs[addr >> 2]; in pxa2xx_pm_read()
129 s->pm_regs[addr >> 2] &= ~(value & 0x2a); in pxa2xx_pm_write()
131 s->pm_regs[addr >> 2] &= ~0x15; in pxa2xx_pm_write()
132 s->pm_regs[addr >> 2] |= value & 0x15; in pxa2xx_pm_write()
138 s->pm_regs[addr >> 2] &= ~value; in pxa2xx_pm_write()
143 s->pm_regs[addr >> 2] = value; in pxa2xx_pm_write()
280 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ in pxa2xx_pwrmode_write()
290 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ in pxa2xx_pwrmode_write()
291 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ in pxa2xx_pwrmode_write()
300 s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2]; in pxa2xx_pwrmode_write()
[all …]
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/arm/
H A Dpxa2xx.c116 return s->pm_regs[addr >> 2]; in pxa2xx_pm_read()
135 s->pm_regs[addr >> 2] &= ~(value & 0x2a); in pxa2xx_pm_write()
137 s->pm_regs[addr >> 2] &= ~0x15; in pxa2xx_pm_write()
138 s->pm_regs[addr >> 2] |= value & 0x15; in pxa2xx_pm_write()
144 s->pm_regs[addr >> 2] &= ~value; in pxa2xx_pm_write()
149 s->pm_regs[addr >> 2] = value; in pxa2xx_pm_write()
291 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ in pxa2xx_pwrmode_write()
301 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ in pxa2xx_pwrmode_write()
302 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ in pxa2xx_pwrmode_write()
311 s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2]; in pxa2xx_pwrmode_write()
[all …]
/dports/emulators/qemu42/qemu-4.2.1/include/hw/arm/
H A Dpxa.h148 uint32_t pm_regs[0x40]; member
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/include/hw/arm/
H A Dpxa.h147 uint32_t pm_regs[0x40]; member
/dports/emulators/qemu-utils/qemu-4.2.1/include/hw/arm/
H A Dpxa.h148 uint32_t pm_regs[0x40]; member
/dports/emulators/qemu-guest-agent/qemu-5.0.1/include/hw/arm/
H A Dpxa.h148 uint32_t pm_regs[0x40]; member
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/include/hw/arm/
H A Dpxa.h148 uint32_t pm_regs[0x40]; member
/dports/emulators/qemu/qemu-6.2.0/include/hw/arm/
H A Dpxa.h156 uint32_t pm_regs[0x40];
/dports/emulators/qemu60/qemu-6.0.0/include/hw/arm/
H A Dpxa.h156 uint32_t pm_regs[0x40]; member
/dports/emulators/qemu5/qemu-5.2.0/include/hw/arm/
H A Dpxa.h156 uint32_t pm_regs[0x40]; member
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/include/hw/arm/
H A Dpxa.h156 uint32_t pm_regs[0x40]; member