| /dports/emulators/qemu-utils/qemu-4.2.1/tcg/ |
| H A D | tcg-op-gvec.c | 1418 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_mov()
1547 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_not()
2252 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_and()
2269 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_or()
2286 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_xor()
2303 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_andc()
2320 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_orc()
2337 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_nand()
2385 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2410 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
[all …]
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| H A D | tcg-op-gvec.h | 104 bool prefer_i64; member
123 bool prefer_i64; member
144 bool prefer_i64; member
165 bool prefer_i64; member
186 bool prefer_i64; member
207 bool prefer_i64; member
|
| /dports/emulators/qemu42/qemu-4.2.1/tcg/ |
| H A D | tcg-op-gvec.c | 1418 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_mov()
1547 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_not()
2252 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_and()
2269 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_or()
2286 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_xor()
2303 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_andc()
2320 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_orc()
2337 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_nand()
2385 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2410 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
[all …]
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| H A D | tcg-op-gvec.h | 104 bool prefer_i64; member
123 bool prefer_i64; member
144 bool prefer_i64; member
165 bool prefer_i64; member
186 bool prefer_i64; member
207 bool prefer_i64; member
|
| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/tcg/ |
| H A D | tcg-op-gvec.c | 364 bool prefer_i64) in choose_vector_type() argument
1248 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_mov()
1365 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_not()
1841 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_and()
1854 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_or()
1867 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_xor()
1880 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_andc()
1893 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_orc()
1903 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
1929 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
[all …]
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| H A D | tcg-op-gvec.h | 101 bool prefer_i64; member
120 bool prefer_i64; member
141 bool prefer_i64; member
162 bool prefer_i64; member
183 bool prefer_i64; member
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| /dports/emulators/qemu5/qemu-5.2.0/tcg/ |
| H A D | tcg-op-gvec.c | 1532 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_mov()
1686 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_not()
2392 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_and()
2409 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_or()
2426 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_xor()
2443 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_andc()
2460 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_orc()
2477 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_nand()
2525 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2550 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
[all …]
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| /dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/tcg/ |
| H A D | tcg-op-gvec.c | 1552 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_mov()
1706 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_not()
2466 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_and()
2483 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_or()
2500 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_xor()
2517 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_andc()
2534 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_orc()
2551 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_nand()
2599 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2623 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
[all …]
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| /dports/emulators/qemu/qemu-6.2.0/tcg/ |
| H A D | tcg-op-gvec.c | 1552 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_mov()
1706 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_not()
2466 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_and()
2483 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_or()
2500 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_xor()
2517 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_andc()
2534 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_orc()
2551 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_nand()
2599 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2623 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
[all …]
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| /dports/emulators/qemu60/qemu-6.0.0/tcg/ |
| H A D | tcg-op-gvec.c | 1552 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_mov()
1706 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_not()
2400 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_and()
2417 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_or()
2434 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_xor()
2451 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_andc()
2468 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_orc()
2485 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_nand()
2533 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2557 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
[all …]
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| /dports/emulators/qemu-guest-agent/qemu-5.0.1/tcg/ |
| H A D | tcg-op-gvec.c | 1450 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_mov()
1579 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_not()
2284 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_and()
2301 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_or()
2318 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_xor()
2335 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_andc()
2352 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_orc()
2369 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_nand()
2417 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2442 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
[all …]
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| /dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/tcg/ |
| H A D | tcg-op-gvec.c | 1450 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_mov()
1579 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_not()
2284 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_and()
2301 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_or()
2318 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_xor()
2335 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_andc()
2352 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_orc()
2369 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_nand()
2417 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
2442 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
[all …]
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| /dports/emulators/qemu60/qemu-6.0.0/include/tcg/ |
| H A D | tcg-op-gvec.h | 111 bool prefer_i64; member
132 bool prefer_i64; member
153 bool prefer_i64; member
174 bool prefer_i64; member
195 bool prefer_i64; member
216 bool prefer_i64; member
|
| /dports/emulators/qemu5/qemu-5.2.0/include/tcg/ |
| H A D | tcg-op-gvec.h | 111 bool prefer_i64; member
132 bool prefer_i64; member
153 bool prefer_i64; member
174 bool prefer_i64; member
195 bool prefer_i64; member
216 bool prefer_i64; member
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/include/tcg/ |
| H A D | tcg-op-gvec.h | 111 bool prefer_i64; member
130 bool prefer_i64; member
151 bool prefer_i64; member
172 bool prefer_i64; member
193 bool prefer_i64; member
214 bool prefer_i64; member
|
| /dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/include/tcg/ |
| H A D | tcg-op-gvec.h | 111 bool prefer_i64; member
130 bool prefer_i64; member
151 bool prefer_i64; member
172 bool prefer_i64; member
193 bool prefer_i64; member
214 bool prefer_i64; member
|
| /dports/emulators/qemu/qemu-6.2.0/include/tcg/ |
| H A D | tcg-op-gvec.h | 111 bool prefer_i64; member
132 bool prefer_i64; member
153 bool prefer_i64; member
174 bool prefer_i64; member
195 bool prefer_i64; member
216 bool prefer_i64; member
|
| /dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/include/tcg/ |
| H A D | tcg-op-gvec.h | 111 bool prefer_i64; member
132 bool prefer_i64; member
153 bool prefer_i64; member
174 bool prefer_i64; member
195 bool prefer_i64; member
216 bool prefer_i64; member
|
| /dports/emulators/qemu5/qemu-5.2.0/target/arm/ |
| H A D | translate.c | 3035 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_ssra()
3111 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_usra()
3221 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_srshr()
3316 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_srsra()
3422 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_urshr()
3536 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_ursra()
3625 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_sri()
3718 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_sli()
3822 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_mla()
3854 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_mls()
[all …]
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| /dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/arm/ |
| H A D | translate.c | 3117 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_ssra()
3193 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_usra()
3309 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_srshr()
3404 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_srsra()
3516 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_urshr()
3630 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_ursra()
3719 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_sri()
3812 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_sli()
3916 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_mla()
3948 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_mls()
[all …]
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| /dports/emulators/qemu/qemu-6.2.0/target/arm/ |
| H A D | translate.c | 3090 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_ssra()
3166 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_usra()
3282 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_srshr()
3377 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_srsra()
3489 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_urshr()
3603 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_ursra()
3692 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_sri()
3785 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_sli()
3889 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_mla()
3921 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_mls()
[all …]
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| /dports/emulators/qemu60/qemu-6.0.0/target/arm/ |
| H A D | translate.c | 3101 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_ssra()
3177 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_usra()
3287 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_srshr()
3382 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_srsra()
3488 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_urshr()
3602 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_ursra()
3691 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_sri()
3784 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_sli()
3888 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_mla()
3920 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_mls()
[all …]
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| /dports/emulators/qemu-utils/qemu-4.2.1/target/arm/ |
| H A D | translate-sve.c | 1128 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_AND_pppp()
1164 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_BIC_pppp()
1194 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_EOR_pppp()
1224 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_SEL_pppp()
1252 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_ORR_pppp()
1282 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_ORN_pppp()
1310 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_NOR_pppp()
1338 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_NAND_pppp()
3329 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_SUBR_zzi()
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| /dports/emulators/qemu-guest-agent/qemu-5.0.1/target/arm/ |
| H A D | translate-sve.c | 1128 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_AND_pppp()
1164 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_BIC_pppp()
1194 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_EOR_pppp()
1224 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_SEL_pppp()
1252 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_ORR_pppp()
1282 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_ORN_pppp()
1310 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_NOR_pppp()
1338 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_NAND_pppp()
3329 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_SUBR_zzi()
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| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/arm/ |
| H A D | translate-sve.c | 1129 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_AND_pppp()
1165 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_BIC_pppp()
1195 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_EOR_pppp()
1225 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_SEL_pppp()
1253 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_ORR_pppp()
1283 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_ORN_pppp()
1311 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_NOR_pppp()
1339 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_NAND_pppp()
3340 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_SUBR_zzi()
|