| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/generic/ |
| H A D | generic_sync_fifo.vhd | 59 rd_i : in std_logic; port
91 rd_i : in std_logic; port in generic_sync_fifo.syn.inferred_sync_fifo
121 rd_i => rd_i,
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| H A D | generic_async_fifo.vhd | 73 rd_i : in std_logic; port
116 rd_i : in std_logic; port in generic_async_fifo.syn.inferred_async_fifo
156 rd_i => rd_i,
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/common/ |
| H A D | generic_shiftreg_fifo.vhd | 64 rd_i : in std_logic; port
99 do_write <= '1' when (rd_i = '1' and we_i = '1')
124 elsif pointer_zero = '1' and rd_i = '1' and we_i = '0' then
138 (we_i = '1' and rd_i = '0' and pointer_full = '0' and empty = '0')
140 (we_i = '0' and rd_i = '1' and pointer_zero = '0')
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| H A D | inferred_sync_fifo.vhd | 59 rd_i : in std_logic; port
85 rd_int <= rd_i and not empty;
104 process(rd_ptr, rd_i, rd_int)
162 elsif(rd_i = '1') then
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| H A D | inferred_async_fifo.vhd | 74 rd_i : in std_logic; port
135 rd_int <= rd_i and not empty_int;
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| /dports/biology/hisat2/hisat2-2.2.1/ |
| H A D | hi_aligner.h | 2972 rd_i -= diff;
2973 int rd_bp = rdseq[rd_i];
2974 if(rd_i < min_rd_i) {
3002 rd_i,
3009 rd_i--;
3092 Edit e(rd_i + 1,
3107 if(rd_i < 0) {
3307 index_t rf_i, rd_i; variable
3342 rd_i++;
3452 if(rd_i == rdlen) {
[all …]
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wbgen2/ |
| H A D | wbgen2_fifo_sync.vhd | 97 rd_i : in std_logic; port in wbgen2_fifo_sync.rtl.generic_sync_fifo
127 rd_i => rd_req_i,
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/ |
| H A D | genram_pkg.vhd | 170 rd_i : in std_logic; port in genram_pkg.generic_async_fifo
197 rd_i : in std_logic; port in genram_pkg.generic_sync_fifo
215 rd_i : in std_logic; port in genram_pkg.generic_shiftreg_fifo
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| /dports/cad/magic/magic-8.3.245/resis/ |
| H A D | ResWrite.c | 145 i_sum += workingDev->te_thist->rd_i;
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| H A D | resis.h | 96 float rd_i; /* Current injected from this device */ member
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_endpoint/ |
| H A D | ep_clock_alignment_fifo.vhd | 103 rd_i => rx_rdreq,
|
| H A D | ep_tx_pcs_16bit.vhd | 234 -- (the rst signal can be set (LOW) only after 4 cycles after rd_i is "unset" (LOW)
292 rd_i => fifo_read_int,
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| H A D | ep_rx_buffer.vhd | 271 rd_i => q_rd,
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| H A D | ep_tx_pcs_8bit.vhd | 249 rd_i => fifo_rd,
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| H A D | ep_rx_path.vhd | 278 rd_i => mbuf_rd,
|
| /dports/cad/openroad/OpenROAD-2.0/src/sta/parasitics/ |
| H A D | ReduceParasitics.cc | 557 double rd_i = findBranchCurrents(drvr_pin, drvr_node, 0, in findMoments() local
559 double rd_volt = rd_i * rd; in findMoments()
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| /dports/graphics/argyllcms/Argyll_V1.9.2/spectro/ |
| H A D | illumread.c | 295 int rd_i = 0, rd_r = 0, rd_p = 0; /* Test mode flags */ in main() local
435 rd_i = 1; in main()
926 if (tmode && rd_i == 0) { in main()
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/fabric/ |
| H A D | xwb_fabric_source.vhd | 106 rd_i => rd,
|
| H A D | xwb_fabric_sink.vhd | 145 rd_i => rd,
|
| /dports/misc/mmv/mmv-1.01b.orig/ |
| H A D | mmv.c | 332 unsigned rd_i; member
2164 prd->rd_i = i; in checkcollisions()
2208 ret = rd1->rd_i - rd2->rd_i;
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_uart/ |
| H A D | wb_simple_uart.vhd | 277 rd_i => fifo_rd,
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_mini_nic/ |
| H A D | wr_mini_nic.vhd | 307 rd_i => tx_fifo_rd,
326 rd_i => rx_fifo_rd,
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/modules/wr_streamers/ |
| H A D | xtx_streamer.vhd | 280 rd_i => tx_fifo_rd,
|
| /dports/textproc/gitlab-elasticsearch-indexer/gitlab-elasticsearch-indexer-ef1440548effec15831eda2d246dacc43233cefb/vendor/github.com/go-enry/go-enry/v2/internal/code-generator/generator/test_files/ |
| H A D | frequencies.gold | 162749 "rd_i": -5.803628,
|