/dports/emulators/riscv-isa-sim/riscv-isa-sim-4f12984/riscv/insns/ |
H A D | viota_m.h | 6 reg_t rd_num = insn.rd(); 11 require_align(rd_num, P.VU.vflmul); 12 require_noover(rd_num, P.VU.vflmul, rs2_num, 1); 32 P.VU.elt<uint8_t>(rd_num, i, true) = use_ori ? 33 P.VU.elt<uint8_t>(rd_num, i) : cnt; 36 P.VU.elt<uint16_t>(rd_num, i, true) = use_ori ? 37 P.VU.elt<uint16_t>(rd_num, i) : cnt; 40 P.VU.elt<uint32_t>(rd_num, i, true) = use_ori ? 41 P.VU.elt<uint32_t>(rd_num, i) : cnt; 44 P.VU.elt<uint64_t>(rd_num, i, true) = use_ori ? [all …]
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H A D | vid_v.h | 6 reg_t rd_num = insn.rd(); 9 require_align(rd_num, P.VU.vflmul); 17 P.VU.elt<uint8_t>(rd_num, i, true) = i; 20 P.VU.elt<uint16_t>(rd_num, i, true) = i; 23 P.VU.elt<uint32_t>(rd_num, i, true) = i; 26 P.VU.elt<uint64_t>(rd_num, i, true) = i;
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H A D | vmv_s_x.h | 8 reg_t rd_num = insn.rd(); 13 P.VU.elt<uint8_t>(rd_num, 0, true) = RS1; 16 P.VU.elt<uint16_t>(rd_num, 0, true) = RS1; 19 P.VU.elt<uint32_t>(rd_num, 0, true) = RS1; 22 P.VU.elt<uint64_t>(rd_num, 0, true) = RS1;
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H A D | vfmv_s_f.h | 12 reg_t rd_num = insn.rd(); 16 P.VU.elt<uint16_t>(rd_num, 0, true) = f16(FRS1).v; 19 P.VU.elt<uint32_t>(rd_num, 0, true) = f32(FRS1).v; 23 P.VU.elt<uint64_t>(rd_num, 0, true) = f64(FRS1).v; 25 P.VU.elt<uint64_t>(rd_num, 0, true) = f32(FRS1).v;
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H A D | vslide1down_vx.h | 31 P.VU.elt<uint8_t>(rd_num, vl - 1, true) = RS1; 34 P.VU.elt<uint16_t>(rd_num, vl - 1, true) = RS1; 37 P.VU.elt<uint32_t>(rd_num, vl - 1, true) = RS1; 40 P.VU.elt<uint64_t>(rd_num, vl - 1, true) = RS1;
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H A D | vslide1up_vx.h | 21 P.VU.elt<uint8_t>(rd_num, 0, true) = RS1; 23 P.VU.elt<uint16_t>(rd_num, 0, true) = RS1; 25 P.VU.elt<uint32_t>(rd_num, 0, true) = RS1; 27 P.VU.elt<uint64_t>(rd_num, 0, true) = RS1;
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H A D | vrgather_vx.h | 12 P.VU.elt<uint8_t>(rd_num, i, true) = rs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint8_t>(rs2_num, rs1); 15 P.VU.elt<uint16_t>(rd_num, i, true) = rs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint16_t>(rs2_num, rs1); 18 P.VU.elt<uint32_t>(rd_num, i, true) = rs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint32_t>(rs2_num, rs1); 21 P.VU.elt<uint64_t>(rd_num, i, true) = rs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint64_t>(rs2_num, rs1);
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H A D | vmulhsu_vx.h | 6 auto &vd = P.VU.elt<int8_t>(rd_num, i, true); 14 auto &vd = P.VU.elt<int16_t>(rd_num, i, true); 22 auto &vd = P.VU.elt<int32_t>(rd_num, i, true); 30 auto &vd = P.VU.elt<int64_t>(rd_num, i, true);
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H A D | vcompress_vm.h | 18 P.VU.elt<uint8_t>(rd_num, pos, true) = P.VU.elt<uint8_t>(rs2_num, i); 21 P.VU.elt<uint16_t>(rd_num, pos, true) = P.VU.elt<uint16_t>(rs2_num, i); 24 P.VU.elt<uint32_t>(rd_num, pos, true) = P.VU.elt<uint32_t>(rs2_num, i); 27 P.VU.elt<uint64_t>(rd_num, pos, true) = P.VU.elt<uint64_t>(rs2_num, i);
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H A D | vrgather_vi.h | 16 … P.VU.elt<uint8_t>(rd_num, i, true) = zimm5 >= P.VU.vlmax ? 0 : P.VU.elt<uint8_t>(rs2_num, zimm5); 19 …P.VU.elt<uint16_t>(rd_num, i, true) = zimm5 >= P.VU.vlmax ? 0 : P.VU.elt<uint16_t>(rs2_num, zimm5); 22 …P.VU.elt<uint32_t>(rd_num, i, true) = zimm5 >= P.VU.vlmax ? 0 : P.VU.elt<uint32_t>(rs2_num, zimm5); 25 …P.VU.elt<uint64_t>(rd_num, i, true) = zimm5 >= P.VU.vlmax ? 0 : P.VU.elt<uint64_t>(rs2_num, zimm5);
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H A D | vmulhsu_vv.h | 6 auto &vd = P.VU.elt<int8_t>(rd_num, i, true); 14 auto &vd = P.VU.elt<int16_t>(rd_num, i, true); 22 auto &vd = P.VU.elt<int32_t>(rd_num, i, true); 30 auto &vd = P.VU.elt<int64_t>(rd_num, i, true);
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H A D | vfcvt_rtz_x_f_v.h | 4 P.VU.elt<int16_t>(rd_num, i) = f16_to_i16(vs2, softfloat_round_minMag, true); 7 P.VU.elt<int32_t>(rd_num, i) = f32_to_i32(vs2, softfloat_round_minMag, true); 10 P.VU.elt<int64_t>(rd_num, i) = f64_to_i64(vs2, softfloat_round_minMag, true);
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H A D | vfcvt_rtz_xu_f_v.h | 4 P.VU.elt<uint16_t>(rd_num, i) = f16_to_ui16(vs2, softfloat_round_minMag, true); 7 P.VU.elt<uint32_t>(rd_num, i) = f32_to_ui32(vs2, softfloat_round_minMag, true); 10 P.VU.elt<uint64_t>(rd_num, i) = f64_to_ui64(vs2, softfloat_round_minMag, true);
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H A D | vrgather_vv.h | 13 P.VU.elt<uint8_t>(rd_num, i, true) = vs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint8_t>(rs2_num, vs1); 18 P.VU.elt<uint16_t>(rd_num, i, true) = vs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint16_t>(rs2_num, vs1); 23 P.VU.elt<uint32_t>(rd_num, i, true) = vs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint32_t>(rs2_num, vs1); 28 P.VU.elt<uint64_t>(rd_num, i, true) = vs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint64_t>(rs2_num, vs1);
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H A D | vfcvt_x_f_v.h | 4 P.VU.elt<int16_t>(rd_num, i) = f16_to_i16(vs2, STATE.frm->read(), true); 7 P.VU.elt<int32_t>(rd_num, i) = f32_to_i32(vs2, STATE.frm->read(), true); 10 P.VU.elt<int64_t>(rd_num, i) = f64_to_i64(vs2, STATE.frm->read(), true);
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H A D | vfcvt_xu_f_v.h | 4 P.VU.elt<uint16_t>(rd_num, i) = f16_to_ui16(vs2, STATE.frm->read(), true); 7 P.VU.elt<uint32_t>(rd_num, i) = f32_to_ui32(vs2, STATE.frm->read(), true); 10 P.VU.elt<uint64_t>(rd_num, i) = f64_to_ui64(vs2, STATE.frm->read(), true);
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H A D | vrgatherei16_vv.h | 15 P.VU.elt<uint8_t>(rd_num, i, true) = vs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint8_t>(rs2_num, vs1); 20 P.VU.elt<uint16_t>(rd_num, i, true) = vs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint16_t>(rs2_num, vs1); 25 P.VU.elt<uint32_t>(rd_num, i, true) = vs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint32_t>(rs2_num, vs1); 30 P.VU.elt<uint64_t>(rd_num, i, true) = vs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint64_t>(rs2_num, vs1);
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H A D | vwmulsu_vv.h | 7 P.VU.elt<uint16_t>(rd_num, i, true) = (int16_t)(int8_t)vs2 * (int16_t)(uint8_t)vs1; 10 P.VU.elt<uint32_t>(rd_num, i, true) = (int32_t)(int16_t)vs2 * (int32_t)(uint16_t)vs1; 13 P.VU.elt<uint64_t>(rd_num, i, true) = (int64_t)(int32_t)vs2 * (int64_t)(uint32_t)vs1;
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H A D | vwmulsu_vx.h | 7 P.VU.elt<uint16_t>(rd_num, i, true) = (int16_t)(int8_t)vs2 * (int16_t)(uint8_t)rs1; 10 P.VU.elt<uint32_t>(rd_num, i, true) = (int32_t)(int16_t)vs2 * (int32_t)(uint16_t)rs1; 13 P.VU.elt<uint64_t>(rd_num, i, true) = (int64_t)(int32_t)vs2 * (int64_t)(uint32_t)rs1;
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H A D | vfslide1up_vf.h | 26 P.VU.elt<float16_t>(rd_num, 0, true) = f16(FRS1); 29 P.VU.elt<float32_t>(rd_num, 0, true) = f32(FRS1); 32 P.VU.elt<float64_t>(rd_num, 0, true) = f64(FRS1);
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H A D | vfslide1down_vf.h | 26 P.VU.elt<float16_t>(rd_num, vl - 1, true) = f16(FRS1); 29 P.VU.elt<float32_t>(rd_num, vl - 1, true) = f32(FRS1); 32 P.VU.elt<float64_t>(rd_num, vl - 1, true) = f64(FRS1);
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H A D | vfwcvt_f_x_v.h | 5 P.VU.elt<float16_t>(rd_num, i, true) = i32_to_f16(vs2); 9 P.VU.elt<float32_t>(rd_num, i, true) = i32_to_f32(vs2); 13 P.VU.elt<float64_t>(rd_num, i, true) = i32_to_f64(vs2);
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H A D | vfwcvt_f_xu_v.h | 5 P.VU.elt<float16_t>(rd_num, i, true) = ui32_to_f16(vs2); 9 P.VU.elt<float32_t>(rd_num, i, true) = ui32_to_f32(vs2); 13 P.VU.elt<float64_t>(rd_num, i, true) = ui32_to_f64(vs2);
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H A D | vfncvt_rtz_x_f_w.h | 5 P.VU.elt<int8_t>(rd_num, i, true) = f16_to_i8(vs2, softfloat_round_minMag, true); 9 P.VU.elt<int16_t>(rd_num, i, true) = f32_to_i16(vs2, softfloat_round_minMag, true); 13 P.VU.elt<int32_t>(rd_num, i, true) = f64_to_i32(vs2, softfloat_round_minMag, true);
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/dports/emulators/riscv-isa-sim/riscv-isa-sim-4f12984/riscv/ |
H A D | decode.h | 615 reg_t rd_num = insn.rd(); \ 640 reg_t rd_num = insn.rd(); \ 949 reg_t rd_num = insn.rd(); \ 980 reg_t rd_num = insn.rd(); \ 1234 P.VU.elt<uint16_t>(rd_num, i, true) = \ 1240 P.VU.elt<uint32_t>(rd_num, i, true) = \ 1299 reg_t rd_num = insn.rd(); \ 1327 reg_t rd_num = insn.rd(); \ 1650 const reg_t rd_num = insn.rd(); \ 1848 reg_t rd_num = insn.rd(); \ [all …]
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