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/dports/emulators/riscv-isa-sim/riscv-isa-sim-4f12984/riscv/insns/
H A Dviota_m.h6 reg_t rd_num = insn.rd();
11 require_align(rd_num, P.VU.vflmul);
12 require_noover(rd_num, P.VU.vflmul, rs2_num, 1);
32 P.VU.elt<uint8_t>(rd_num, i, true) = use_ori ?
33 P.VU.elt<uint8_t>(rd_num, i) : cnt;
36 P.VU.elt<uint16_t>(rd_num, i, true) = use_ori ?
37 P.VU.elt<uint16_t>(rd_num, i) : cnt;
40 P.VU.elt<uint32_t>(rd_num, i, true) = use_ori ?
41 P.VU.elt<uint32_t>(rd_num, i) : cnt;
44 P.VU.elt<uint64_t>(rd_num, i, true) = use_ori ?
[all …]
H A Dvid_v.h6 reg_t rd_num = insn.rd();
9 require_align(rd_num, P.VU.vflmul);
17 P.VU.elt<uint8_t>(rd_num, i, true) = i;
20 P.VU.elt<uint16_t>(rd_num, i, true) = i;
23 P.VU.elt<uint32_t>(rd_num, i, true) = i;
26 P.VU.elt<uint64_t>(rd_num, i, true) = i;
H A Dvmv_s_x.h8 reg_t rd_num = insn.rd();
13 P.VU.elt<uint8_t>(rd_num, 0, true) = RS1;
16 P.VU.elt<uint16_t>(rd_num, 0, true) = RS1;
19 P.VU.elt<uint32_t>(rd_num, 0, true) = RS1;
22 P.VU.elt<uint64_t>(rd_num, 0, true) = RS1;
H A Dvfmv_s_f.h12 reg_t rd_num = insn.rd();
16 P.VU.elt<uint16_t>(rd_num, 0, true) = f16(FRS1).v;
19 P.VU.elt<uint32_t>(rd_num, 0, true) = f32(FRS1).v;
23 P.VU.elt<uint64_t>(rd_num, 0, true) = f64(FRS1).v;
25 P.VU.elt<uint64_t>(rd_num, 0, true) = f32(FRS1).v;
H A Dvslide1down_vx.h31 P.VU.elt<uint8_t>(rd_num, vl - 1, true) = RS1;
34 P.VU.elt<uint16_t>(rd_num, vl - 1, true) = RS1;
37 P.VU.elt<uint32_t>(rd_num, vl - 1, true) = RS1;
40 P.VU.elt<uint64_t>(rd_num, vl - 1, true) = RS1;
H A Dvslide1up_vx.h21 P.VU.elt<uint8_t>(rd_num, 0, true) = RS1;
23 P.VU.elt<uint16_t>(rd_num, 0, true) = RS1;
25 P.VU.elt<uint32_t>(rd_num, 0, true) = RS1;
27 P.VU.elt<uint64_t>(rd_num, 0, true) = RS1;
H A Dvrgather_vx.h12 P.VU.elt<uint8_t>(rd_num, i, true) = rs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint8_t>(rs2_num, rs1);
15 P.VU.elt<uint16_t>(rd_num, i, true) = rs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint16_t>(rs2_num, rs1);
18 P.VU.elt<uint32_t>(rd_num, i, true) = rs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint32_t>(rs2_num, rs1);
21 P.VU.elt<uint64_t>(rd_num, i, true) = rs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint64_t>(rs2_num, rs1);
H A Dvmulhsu_vx.h6 auto &vd = P.VU.elt<int8_t>(rd_num, i, true);
14 auto &vd = P.VU.elt<int16_t>(rd_num, i, true);
22 auto &vd = P.VU.elt<int32_t>(rd_num, i, true);
30 auto &vd = P.VU.elt<int64_t>(rd_num, i, true);
H A Dvcompress_vm.h18 P.VU.elt<uint8_t>(rd_num, pos, true) = P.VU.elt<uint8_t>(rs2_num, i);
21 P.VU.elt<uint16_t>(rd_num, pos, true) = P.VU.elt<uint16_t>(rs2_num, i);
24 P.VU.elt<uint32_t>(rd_num, pos, true) = P.VU.elt<uint32_t>(rs2_num, i);
27 P.VU.elt<uint64_t>(rd_num, pos, true) = P.VU.elt<uint64_t>(rs2_num, i);
H A Dvrgather_vi.h16 … P.VU.elt<uint8_t>(rd_num, i, true) = zimm5 >= P.VU.vlmax ? 0 : P.VU.elt<uint8_t>(rs2_num, zimm5);
19 …P.VU.elt<uint16_t>(rd_num, i, true) = zimm5 >= P.VU.vlmax ? 0 : P.VU.elt<uint16_t>(rs2_num, zimm5);
22 …P.VU.elt<uint32_t>(rd_num, i, true) = zimm5 >= P.VU.vlmax ? 0 : P.VU.elt<uint32_t>(rs2_num, zimm5);
25 …P.VU.elt<uint64_t>(rd_num, i, true) = zimm5 >= P.VU.vlmax ? 0 : P.VU.elt<uint64_t>(rs2_num, zimm5);
H A Dvmulhsu_vv.h6 auto &vd = P.VU.elt<int8_t>(rd_num, i, true);
14 auto &vd = P.VU.elt<int16_t>(rd_num, i, true);
22 auto &vd = P.VU.elt<int32_t>(rd_num, i, true);
30 auto &vd = P.VU.elt<int64_t>(rd_num, i, true);
H A Dvfcvt_rtz_x_f_v.h4 P.VU.elt<int16_t>(rd_num, i) = f16_to_i16(vs2, softfloat_round_minMag, true);
7 P.VU.elt<int32_t>(rd_num, i) = f32_to_i32(vs2, softfloat_round_minMag, true);
10 P.VU.elt<int64_t>(rd_num, i) = f64_to_i64(vs2, softfloat_round_minMag, true);
H A Dvfcvt_rtz_xu_f_v.h4 P.VU.elt<uint16_t>(rd_num, i) = f16_to_ui16(vs2, softfloat_round_minMag, true);
7 P.VU.elt<uint32_t>(rd_num, i) = f32_to_ui32(vs2, softfloat_round_minMag, true);
10 P.VU.elt<uint64_t>(rd_num, i) = f64_to_ui64(vs2, softfloat_round_minMag, true);
H A Dvrgather_vv.h13 P.VU.elt<uint8_t>(rd_num, i, true) = vs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint8_t>(rs2_num, vs1);
18 P.VU.elt<uint16_t>(rd_num, i, true) = vs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint16_t>(rs2_num, vs1);
23 P.VU.elt<uint32_t>(rd_num, i, true) = vs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint32_t>(rs2_num, vs1);
28 P.VU.elt<uint64_t>(rd_num, i, true) = vs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint64_t>(rs2_num, vs1);
H A Dvfcvt_x_f_v.h4 P.VU.elt<int16_t>(rd_num, i) = f16_to_i16(vs2, STATE.frm->read(), true);
7 P.VU.elt<int32_t>(rd_num, i) = f32_to_i32(vs2, STATE.frm->read(), true);
10 P.VU.elt<int64_t>(rd_num, i) = f64_to_i64(vs2, STATE.frm->read(), true);
H A Dvfcvt_xu_f_v.h4 P.VU.elt<uint16_t>(rd_num, i) = f16_to_ui16(vs2, STATE.frm->read(), true);
7 P.VU.elt<uint32_t>(rd_num, i) = f32_to_ui32(vs2, STATE.frm->read(), true);
10 P.VU.elt<uint64_t>(rd_num, i) = f64_to_ui64(vs2, STATE.frm->read(), true);
H A Dvrgatherei16_vv.h15 P.VU.elt<uint8_t>(rd_num, i, true) = vs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint8_t>(rs2_num, vs1);
20 P.VU.elt<uint16_t>(rd_num, i, true) = vs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint16_t>(rs2_num, vs1);
25 P.VU.elt<uint32_t>(rd_num, i, true) = vs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint32_t>(rs2_num, vs1);
30 P.VU.elt<uint64_t>(rd_num, i, true) = vs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint64_t>(rs2_num, vs1);
H A Dvwmulsu_vv.h7 P.VU.elt<uint16_t>(rd_num, i, true) = (int16_t)(int8_t)vs2 * (int16_t)(uint8_t)vs1;
10 P.VU.elt<uint32_t>(rd_num, i, true) = (int32_t)(int16_t)vs2 * (int32_t)(uint16_t)vs1;
13 P.VU.elt<uint64_t>(rd_num, i, true) = (int64_t)(int32_t)vs2 * (int64_t)(uint32_t)vs1;
H A Dvwmulsu_vx.h7 P.VU.elt<uint16_t>(rd_num, i, true) = (int16_t)(int8_t)vs2 * (int16_t)(uint8_t)rs1;
10 P.VU.elt<uint32_t>(rd_num, i, true) = (int32_t)(int16_t)vs2 * (int32_t)(uint16_t)rs1;
13 P.VU.elt<uint64_t>(rd_num, i, true) = (int64_t)(int32_t)vs2 * (int64_t)(uint32_t)rs1;
H A Dvfslide1up_vf.h26 P.VU.elt<float16_t>(rd_num, 0, true) = f16(FRS1);
29 P.VU.elt<float32_t>(rd_num, 0, true) = f32(FRS1);
32 P.VU.elt<float64_t>(rd_num, 0, true) = f64(FRS1);
H A Dvfslide1down_vf.h26 P.VU.elt<float16_t>(rd_num, vl - 1, true) = f16(FRS1);
29 P.VU.elt<float32_t>(rd_num, vl - 1, true) = f32(FRS1);
32 P.VU.elt<float64_t>(rd_num, vl - 1, true) = f64(FRS1);
H A Dvfwcvt_f_x_v.h5 P.VU.elt<float16_t>(rd_num, i, true) = i32_to_f16(vs2);
9 P.VU.elt<float32_t>(rd_num, i, true) = i32_to_f32(vs2);
13 P.VU.elt<float64_t>(rd_num, i, true) = i32_to_f64(vs2);
H A Dvfwcvt_f_xu_v.h5 P.VU.elt<float16_t>(rd_num, i, true) = ui32_to_f16(vs2);
9 P.VU.elt<float32_t>(rd_num, i, true) = ui32_to_f32(vs2);
13 P.VU.elt<float64_t>(rd_num, i, true) = ui32_to_f64(vs2);
H A Dvfncvt_rtz_x_f_w.h5 P.VU.elt<int8_t>(rd_num, i, true) = f16_to_i8(vs2, softfloat_round_minMag, true);
9 P.VU.elt<int16_t>(rd_num, i, true) = f32_to_i16(vs2, softfloat_round_minMag, true);
13 P.VU.elt<int32_t>(rd_num, i, true) = f64_to_i32(vs2, softfloat_round_minMag, true);
/dports/emulators/riscv-isa-sim/riscv-isa-sim-4f12984/riscv/
H A Ddecode.h615 reg_t rd_num = insn.rd(); \
640 reg_t rd_num = insn.rd(); \
949 reg_t rd_num = insn.rd(); \
980 reg_t rd_num = insn.rd(); \
1234 P.VU.elt<uint16_t>(rd_num, i, true) = \
1240 P.VU.elt<uint32_t>(rd_num, i, true) = \
1299 reg_t rd_num = insn.rd(); \
1327 reg_t rd_num = insn.rd(); \
1650 const reg_t rd_num = insn.rd(); \
1848 reg_t rd_num = insn.rd(); \
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