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Searched refs:reg_equiv_init (Results 1 – 25 of 176) sorted by relevance

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/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/gcc-4.1-20060728/gcc/
H A Dlocal-alloc.c803 reg_equiv_init = ggc_alloc_cleared (max_regno * sizeof (rtx)); in update_equiv_regs()
869 reg_equiv_init[regno] in update_equiv_regs()
870 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[regno]); in update_equiv_regs()
966 reg_equiv_init[regno] in update_equiv_regs()
967 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[regno]); in update_equiv_regs()
1067 reg_equiv_init[regno] in update_equiv_regs()
1166 reg_equiv_init[regno] = NULL_RTX; in update_equiv_regs()
1199 reg_equiv_init[regno] in update_equiv_regs()
1268 reg_equiv_init[regno] = NULL_RTX; in no_equiv()
H A Dreload.h176 extern GTY((length("reg_equiv_init_size"))) rtx *reg_equiv_init;
H A Dreload1.c128 rtx *reg_equiv_init; variable
787 reg_equiv_init[i] = NULL_RTX; in reload()
792 reg_equiv_init[i] = NULL_RTX; in reload()
797 reg_equiv_init[i] = NULL_RTX; in reload()
803 if (reg_equiv_init[i]) in reload()
806 print_inline_rtx (dump_file, reg_equiv_init[i], 20); in reload()
948 reg_equiv_init[i] = 0; in reload()
1043 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0) in reload()
1262 reg_equiv_init = 0; in reload()
1470 && reg_equiv_init[REGNO (SET_DEST (set))]) in calculate_needs_all_insns()
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/dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/
H A Dreload.h258 #define reg_equiv_init(ELT) \ macro
/dports/devel/riscv64-gcc/gcc-8.3.0/gcc/
H A Dreload.h258 #define reg_equiv_init(ELT) \ macro
/dports/lang/gnat_util/gcc-6-20180516/gcc/
H A Dreload.h257 #define reg_equiv_init(ELT) \ macro
/dports/lang/gcc48/gcc-4.8.5/gcc/
H A Dreload.h255 #define reg_equiv_init(ELT) \ macro
/dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/
H A Dreload.h258 #define reg_equiv_init(ELT) \ macro
/dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/
H A Dreload.h258 #define reg_equiv_init(ELT) \ macro
/dports/devel/arm-none-eabi-gcc492/gcc-4.9.2/gcc/
H A Dreload.h255 #define reg_equiv_init(ELT) \ macro
/dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/
H A Dreload.h258 #define reg_equiv_init(ELT) \ macro
/dports/lang/gcc9-aux/gcc-9.1.0/gcc/
H A Dreload.h258 #define reg_equiv_init(ELT) \ macro
/dports/lang/gcc9-devel/gcc-9-20211007/gcc/
H A Dreload.h258 #define reg_equiv_init(ELT) \ macro
/dports/lang/gcc8/gcc-8.5.0/gcc/
H A Dreload.h258 #define reg_equiv_init(ELT) \ macro
/dports/lang/gcc9/gcc-9.4.0/gcc/
H A Dreload.h258 #define reg_equiv_init(ELT) \ macro
/dports/devel/mingw32-gcc/gcc-4.8.1/gcc/
H A Dreload.h255 #define reg_equiv_init(ELT) \ macro
/dports/lang/gcc6-aux/gcc-6-20180516/gcc/
H A Dreload.h257 #define reg_equiv_init(ELT) \ macro
/dports/lang/gcc12-devel/gcc-12-20211205/gcc/
H A Dreload.h258 #define reg_equiv_init(ELT) \ macro
H A Dreload1.c681 if (reg_renumber[i] < 0 && reg_equiv_init (i) != 0) in remove_init_insns()
947 reg_equiv_init (i) = 0; in reload()
1588 rtx_insn_list *init = reg_equiv_init (regno); in calculate_elim_costs_all_insns()
1615 if (reg_equiv_init (i)) in calculate_elim_costs_all_insns()
2137 || reg_equiv_init (i) == 0) in alter_reg()
2477 && reg_equiv_init (REGNO (x)) in note_reg_elim_costly()
2570 reg_equiv_init (regno) = NULL; in eliminate_regs_1()
4098 reg_equiv_init (i) = NULL; in init_eliminable_invariants()
4103 reg_equiv_init (i) = NULL; in init_eliminable_invariants()
4108 reg_equiv_init (i) = NULL; in init_eliminable_invariants()
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/dports/devel/avr-gcc/gcc-10.2.0/gcc/
H A Dreload.h258 #define reg_equiv_init(ELT) \ macro
/dports/lang/gcc11-devel/gcc-11-20211009/gcc/
H A Dreload.h258 #define reg_equiv_init(ELT) \ macro
/dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/
H A Dreload.h258 #define reg_equiv_init(ELT) \ macro
/dports/lang/gcc10/gcc-10.3.0/gcc/
H A Dreload.h258 #define reg_equiv_init(ELT) \ macro
/dports/lang/gcc11/gcc-11.2.0/gcc/
H A Dreload.h258 #define reg_equiv_init(ELT) \ macro
/dports/lang/gcc10-devel/gcc-10-20211008/gcc/
H A Dreload.h258 #define reg_equiv_init(ELT) \ macro

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