reg_offset (reference) in projects: dports

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Searched refs:reg_offset (Results 1 – 25 of 1957) sorted by relevance

12 3 4 5 6 7 8 9 10 >>...79

/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/mfd/
H A D	sec-irq.c	`22 .reg_offset = 0, 26 .reg_offset = 0, 30 .reg_offset = 0, 34 .reg_offset = 0, 38 .reg_offset = 0, 42 .reg_offset = 0, 46 .reg_offset = 0, 50 .reg_offset = 0, 54 .reg_offset = 1, 58 .reg_offset = 1, [all …]`
H A D	da9052-irq.c	`37 .reg_offset = 0, 41 .reg_offset = 0, 45 .reg_offset = 0, 49 .reg_offset = 0, 53 .reg_offset = 0, 57 .reg_offset = 0, 61 .reg_offset = 0, 65 .reg_offset = 0, 69 .reg_offset = 1, 73 .reg_offset = 1, [all …]`
H A D	wm5110-tables.c	328 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ8_EINT1 331 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ7_EINT1 334 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ6_EINT1 337 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ5_EINT1 340 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ4_EINT1 343 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ3_EINT1 346 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1 359 .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1 362 .reg_offset = 2, .mask = ARIZONA_MICDET_EINT1 519 .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1 [all …]
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/mfd/
H A D	sec-irq.c	`22 .reg_offset = 0, 26 .reg_offset = 0, 30 .reg_offset = 0, 34 .reg_offset = 0, 38 .reg_offset = 0, 42 .reg_offset = 0, 46 .reg_offset = 0, 50 .reg_offset = 0, 54 .reg_offset = 1, 58 .reg_offset = 1, [all …]`
H A D	da9052-irq.c	`37 .reg_offset = 0, 41 .reg_offset = 0, 45 .reg_offset = 0, 49 .reg_offset = 0, 53 .reg_offset = 0, 57 .reg_offset = 0, 61 .reg_offset = 0, 65 .reg_offset = 0, 69 .reg_offset = 1, 73 .reg_offset = 1, [all …]`
H A D	wm5110-tables.c	328 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ8_EINT1 331 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ7_EINT1 334 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ6_EINT1 337 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ5_EINT1 340 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ4_EINT1 343 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ3_EINT1 346 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1 359 .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1 362 .reg_offset = 2, .mask = ARIZONA_MICDET_EINT1 519 .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1 [all …]
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/mfd/
H A D	sec-irq.c	`22 .reg_offset = 0, 26 .reg_offset = 0, 30 .reg_offset = 0, 34 .reg_offset = 0, 38 .reg_offset = 0, 42 .reg_offset = 0, 46 .reg_offset = 0, 50 .reg_offset = 0, 54 .reg_offset = 1, 58 .reg_offset = 1, [all …]`
H A D	da9052-irq.c	`37 .reg_offset = 0, 41 .reg_offset = 0, 45 .reg_offset = 0, 49 .reg_offset = 0, 53 .reg_offset = 0, 57 .reg_offset = 0, 61 .reg_offset = 0, 65 .reg_offset = 0, 69 .reg_offset = 1, 73 .reg_offset = 1, [all …]`
H A D	wm5110-tables.c	328 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ8_EINT1 331 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ7_EINT1 334 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ6_EINT1 337 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ5_EINT1 340 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ4_EINT1 343 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ3_EINT1 346 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1 359 .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1 362 .reg_offset = 2, .mask = ARIZONA_MICDET_EINT1 519 .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1 [all …]
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A D	arct_reg_init.c	34 adev->reg_offset[GC_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in arct_reg_base_init() 35 adev->reg_offset[HDP_HWIP][i] = (uint32_t )(&(HDP_BASE.instance[i])); in arct_reg_base_init() 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t )(&(MMHUB_BASE.instance[i])); in arct_reg_base_init() 38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t )(&(NBIF0_BASE.instance[i])); in arct_reg_base_init() 39 adev->reg_offset[MP0_HWIP][i] = (uint32_t )(&(MP0_BASE.instance[i])); in arct_reg_base_init() 40 adev->reg_offset[MP1_HWIP][i] = (uint32_t )(&(MP1_BASE.instance[i])); in arct_reg_base_init() 41 adev->reg_offset[UVD_HWIP][i] = (uint32_t )(&(UVD_BASE.instance[i])); in arct_reg_base_init() 42 adev->reg_offset[DF_HWIP][i] = (uint32_t )(&(DF_BASE.instance[i])); in arct_reg_base_init() 53 adev->reg_offset[THM_HWIP][i] = (uint32_t )(&(THM_BASE.instance[i])); in arct_reg_base_init() 54 adev->reg_offset[UMC_HWIP][i] = (uint32_t )(&(UMC_BASE.instance[i])); in arct_reg_base_init() [all …]
H A D	aldebaran_reg_init.c	34 adev->reg_offset[GC_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in aldebaran_reg_base_init() 35 adev->reg_offset[HDP_HWIP][i] = (uint32_t )(&(HDP_BASE.instance[i])); in aldebaran_reg_base_init() 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t )(&(MMHUB_BASE.instance[i])); in aldebaran_reg_base_init() 37 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t )(&(ATHUB_BASE.instance[i])); in aldebaran_reg_base_init() 38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t )(&(NBIO_BASE.instance[i])); in aldebaran_reg_base_init() 39 adev->reg_offset[MP0_HWIP][i] = (uint32_t )(&(MP0_BASE.instance[i])); in aldebaran_reg_base_init() 40 adev->reg_offset[MP1_HWIP][i] = (uint32_t )(&(MP1_BASE.instance[i])); in aldebaran_reg_base_init() 41 adev->reg_offset[DF_HWIP][i] = (uint32_t )(&(DF_BASE.instance[i])); in aldebaran_reg_base_init() 49 adev->reg_offset[THM_HWIP][i] = (uint32_t )(&(THM_BASE.instance[i])); in aldebaran_reg_base_init() 50 adev->reg_offset[UMC_HWIP][i] = (uint32_t )(&(UMC_BASE.instance[i])); in aldebaran_reg_base_init() [all …]
H A D	dimgrey_cavefish_reg_init.c	35 adev->reg_offset[GC_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in dimgrey_cavefish_reg_base_init() 36 adev->reg_offset[HDP_HWIP][i] = (uint32_t )(&(HDP_BASE.instance[i])); in dimgrey_cavefish_reg_base_init() 40 adev->reg_offset[MP0_HWIP][i] = (uint32_t )(&(MP0_BASE.instance[i])); in dimgrey_cavefish_reg_base_init() 41 adev->reg_offset[MP1_HWIP][i] = (uint32_t )(&(MP1_BASE.instance[i])); in dimgrey_cavefish_reg_base_init() 42 adev->reg_offset[VCN_HWIP][i] = (uint32_t )(&(VCN0_BASE.instance[i])); in dimgrey_cavefish_reg_base_init() 43 adev->reg_offset[DF_HWIP][i] = (uint32_t )(&(DF_BASE.instance[i])); in dimgrey_cavefish_reg_base_init() 44 adev->reg_offset[DCE_HWIP][i] = (uint32_t )(&(DCN_BASE.instance[i])); in dimgrey_cavefish_reg_base_init() 46 adev->reg_offset[SDMA0_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in dimgrey_cavefish_reg_base_init() 47 adev->reg_offset[SDMA1_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in dimgrey_cavefish_reg_base_init() 48 adev->reg_offset[SDMA2_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in dimgrey_cavefish_reg_base_init() [all …]
H A D	sienna_cichlid_reg_init.c	35 adev->reg_offset[GC_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in sienna_cichlid_reg_base_init() 36 adev->reg_offset[HDP_HWIP][i] = (uint32_t )(&(HDP_BASE.instance[i])); in sienna_cichlid_reg_base_init() 40 adev->reg_offset[MP0_HWIP][i] = (uint32_t )(&(MP0_BASE.instance[i])); in sienna_cichlid_reg_base_init() 41 adev->reg_offset[MP1_HWIP][i] = (uint32_t )(&(MP1_BASE.instance[i])); in sienna_cichlid_reg_base_init() 42 adev->reg_offset[VCN_HWIP][i] = (uint32_t )(&(VCN_BASE.instance[i])); in sienna_cichlid_reg_base_init() 43 adev->reg_offset[DF_HWIP][i] = (uint32_t )(&(DF_BASE.instance[i])); in sienna_cichlid_reg_base_init() 44 adev->reg_offset[DCE_HWIP][i] = (uint32_t )(&(DCN_BASE.instance[i])); in sienna_cichlid_reg_base_init() 46 adev->reg_offset[SDMA0_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in sienna_cichlid_reg_base_init() 47 adev->reg_offset[SDMA1_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in sienna_cichlid_reg_base_init() 48 adev->reg_offset[SDMA2_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in sienna_cichlid_reg_base_init() [all …]
H A D	navi14_reg_init.c	34 adev->reg_offset[GC_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in navi14_reg_base_init() 35 adev->reg_offset[HDP_HWIP][i] = (uint32_t )(&(HDP_BASE.instance[i])); in navi14_reg_base_init() 39 adev->reg_offset[MP0_HWIP][i] = (uint32_t )(&(MP0_BASE.instance[i])); in navi14_reg_base_init() 40 adev->reg_offset[MP1_HWIP][i] = (uint32_t )(&(MP1_BASE.instance[i])); in navi14_reg_base_init() 41 adev->reg_offset[VCN_HWIP][i] = (uint32_t )(&(UVD0_BASE.instance[i])); in navi14_reg_base_init() 42 adev->reg_offset[DF_HWIP][i] = (uint32_t )(&(DF_BASE.instance[i])); in navi14_reg_base_init() 43 adev->reg_offset[DCE_HWIP][i] = (uint32_t )(&(DMU_BASE.instance[i])); in navi14_reg_base_init() 45 adev->reg_offset[SDMA0_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in navi14_reg_base_init() 46 adev->reg_offset[SDMA1_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in navi14_reg_base_init() 48 adev->reg_offset[THM_HWIP][i] = (uint32_t )(&(THM_BASE.instance[i])); in navi14_reg_base_init() [all …]
H A D	navi12_reg_init.c	34 adev->reg_offset[GC_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in navi12_reg_base_init() 35 adev->reg_offset[HDP_HWIP][i] = (uint32_t )(&(HDP_BASE.instance[i])); in navi12_reg_base_init() 39 adev->reg_offset[MP0_HWIP][i] = (uint32_t )(&(MP0_BASE.instance[i])); in navi12_reg_base_init() 40 adev->reg_offset[MP1_HWIP][i] = (uint32_t )(&(MP1_BASE.instance[i])); in navi12_reg_base_init() 41 adev->reg_offset[VCN_HWIP][i] = (uint32_t )(&(UVD0_BASE.instance[i])); in navi12_reg_base_init() 42 adev->reg_offset[DF_HWIP][i] = (uint32_t )(&(DF_BASE.instance[i])); in navi12_reg_base_init() 43 adev->reg_offset[DCE_HWIP][i] = (uint32_t )(&(DMU_BASE.instance[i])); in navi12_reg_base_init() 45 adev->reg_offset[SDMA0_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in navi12_reg_base_init() 46 adev->reg_offset[SDMA1_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in navi12_reg_base_init() 48 adev->reg_offset[THM_HWIP][i] = (uint32_t )(&(THM_BASE.instance[i])); in navi12_reg_base_init() [all …]
H A D	navi10_reg_init.c	34 adev->reg_offset[GC_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in navi10_reg_base_init() 35 adev->reg_offset[HDP_HWIP][i] = (uint32_t )(&(HDP_BASE.instance[i])); in navi10_reg_base_init() 39 adev->reg_offset[MP0_HWIP][i] = (uint32_t )(&(MP0_BASE.instance[i])); in navi10_reg_base_init() 40 adev->reg_offset[MP1_HWIP][i] = (uint32_t )(&(MP1_BASE.instance[i])); in navi10_reg_base_init() 41 adev->reg_offset[VCN_HWIP][i] = (uint32_t )(&(VCN_BASE.instance[i])); in navi10_reg_base_init() 42 adev->reg_offset[DF_HWIP][i] = (uint32_t )(&(DF_BASE.instance[i])); in navi10_reg_base_init() 43 adev->reg_offset[DCE_HWIP][i] = (uint32_t )(&(DCN_BASE.instance[i])); in navi10_reg_base_init() 45 adev->reg_offset[SDMA0_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in navi10_reg_base_init() 46 adev->reg_offset[SDMA1_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in navi10_reg_base_init() 48 adev->reg_offset[THM_HWIP][i] = (uint32_t )(&(THM_BASE.instance[i])); in navi10_reg_base_init() [all …]
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A D	arct_reg_init.c	34 adev->reg_offset[GC_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in arct_reg_base_init() 35 adev->reg_offset[HDP_HWIP][i] = (uint32_t )(&(HDP_BASE.instance[i])); in arct_reg_base_init() 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t )(&(MMHUB_BASE.instance[i])); in arct_reg_base_init() 38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t )(&(NBIF0_BASE.instance[i])); in arct_reg_base_init() 39 adev->reg_offset[MP0_HWIP][i] = (uint32_t )(&(MP0_BASE.instance[i])); in arct_reg_base_init() 40 adev->reg_offset[MP1_HWIP][i] = (uint32_t )(&(MP1_BASE.instance[i])); in arct_reg_base_init() 41 adev->reg_offset[UVD_HWIP][i] = (uint32_t )(&(UVD_BASE.instance[i])); in arct_reg_base_init() 42 adev->reg_offset[DF_HWIP][i] = (uint32_t )(&(DF_BASE.instance[i])); in arct_reg_base_init() 53 adev->reg_offset[THM_HWIP][i] = (uint32_t )(&(THM_BASE.instance[i])); in arct_reg_base_init() 54 adev->reg_offset[UMC_HWIP][i] = (uint32_t )(&(UMC_BASE.instance[i])); in arct_reg_base_init() [all …]
H A D	aldebaran_reg_init.c	34 adev->reg_offset[GC_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in aldebaran_reg_base_init() 35 adev->reg_offset[HDP_HWIP][i] = (uint32_t )(&(HDP_BASE.instance[i])); in aldebaran_reg_base_init() 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t )(&(MMHUB_BASE.instance[i])); in aldebaran_reg_base_init() 37 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t )(&(ATHUB_BASE.instance[i])); in aldebaran_reg_base_init() 38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t )(&(NBIO_BASE.instance[i])); in aldebaran_reg_base_init() 39 adev->reg_offset[MP0_HWIP][i] = (uint32_t )(&(MP0_BASE.instance[i])); in aldebaran_reg_base_init() 40 adev->reg_offset[MP1_HWIP][i] = (uint32_t )(&(MP1_BASE.instance[i])); in aldebaran_reg_base_init() 41 adev->reg_offset[DF_HWIP][i] = (uint32_t )(&(DF_BASE.instance[i])); in aldebaran_reg_base_init() 49 adev->reg_offset[THM_HWIP][i] = (uint32_t )(&(THM_BASE.instance[i])); in aldebaran_reg_base_init() 50 adev->reg_offset[UMC_HWIP][i] = (uint32_t )(&(UMC_BASE.instance[i])); in aldebaran_reg_base_init() [all …]
H A D	dimgrey_cavefish_reg_init.c	35 adev->reg_offset[GC_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in dimgrey_cavefish_reg_base_init() 36 adev->reg_offset[HDP_HWIP][i] = (uint32_t )(&(HDP_BASE.instance[i])); in dimgrey_cavefish_reg_base_init() 40 adev->reg_offset[MP0_HWIP][i] = (uint32_t )(&(MP0_BASE.instance[i])); in dimgrey_cavefish_reg_base_init() 41 adev->reg_offset[MP1_HWIP][i] = (uint32_t )(&(MP1_BASE.instance[i])); in dimgrey_cavefish_reg_base_init() 42 adev->reg_offset[VCN_HWIP][i] = (uint32_t )(&(VCN0_BASE.instance[i])); in dimgrey_cavefish_reg_base_init() 43 adev->reg_offset[DF_HWIP][i] = (uint32_t )(&(DF_BASE.instance[i])); in dimgrey_cavefish_reg_base_init() 44 adev->reg_offset[DCE_HWIP][i] = (uint32_t )(&(DCN_BASE.instance[i])); in dimgrey_cavefish_reg_base_init() 46 adev->reg_offset[SDMA0_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in dimgrey_cavefish_reg_base_init() 47 adev->reg_offset[SDMA1_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in dimgrey_cavefish_reg_base_init() 48 adev->reg_offset[SDMA2_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in dimgrey_cavefish_reg_base_init() [all …]
H A D	sienna_cichlid_reg_init.c	35 adev->reg_offset[GC_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in sienna_cichlid_reg_base_init() 36 adev->reg_offset[HDP_HWIP][i] = (uint32_t )(&(HDP_BASE.instance[i])); in sienna_cichlid_reg_base_init() 40 adev->reg_offset[MP0_HWIP][i] = (uint32_t )(&(MP0_BASE.instance[i])); in sienna_cichlid_reg_base_init() 41 adev->reg_offset[MP1_HWIP][i] = (uint32_t )(&(MP1_BASE.instance[i])); in sienna_cichlid_reg_base_init() 42 adev->reg_offset[VCN_HWIP][i] = (uint32_t )(&(VCN_BASE.instance[i])); in sienna_cichlid_reg_base_init() 43 adev->reg_offset[DF_HWIP][i] = (uint32_t )(&(DF_BASE.instance[i])); in sienna_cichlid_reg_base_init() 44 adev->reg_offset[DCE_HWIP][i] = (uint32_t )(&(DCN_BASE.instance[i])); in sienna_cichlid_reg_base_init() 46 adev->reg_offset[SDMA0_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in sienna_cichlid_reg_base_init() 47 adev->reg_offset[SDMA1_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in sienna_cichlid_reg_base_init() 48 adev->reg_offset[SDMA2_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in sienna_cichlid_reg_base_init() [all …]
H A D	navi10_reg_init.c	34 adev->reg_offset[GC_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in navi10_reg_base_init() 35 adev->reg_offset[HDP_HWIP][i] = (uint32_t )(&(HDP_BASE.instance[i])); in navi10_reg_base_init() 39 adev->reg_offset[MP0_HWIP][i] = (uint32_t )(&(MP0_BASE.instance[i])); in navi10_reg_base_init() 40 adev->reg_offset[MP1_HWIP][i] = (uint32_t )(&(MP1_BASE.instance[i])); in navi10_reg_base_init() 41 adev->reg_offset[VCN_HWIP][i] = (uint32_t )(&(VCN_BASE.instance[i])); in navi10_reg_base_init() 42 adev->reg_offset[DF_HWIP][i] = (uint32_t )(&(DF_BASE.instance[i])); in navi10_reg_base_init() 43 adev->reg_offset[DCE_HWIP][i] = (uint32_t )(&(DCN_BASE.instance[i])); in navi10_reg_base_init() 45 adev->reg_offset[SDMA0_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in navi10_reg_base_init() 46 adev->reg_offset[SDMA1_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in navi10_reg_base_init() 48 adev->reg_offset[THM_HWIP][i] = (uint32_t )(&(THM_BASE.instance[i])); in navi10_reg_base_init() [all …]
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A D	arct_reg_init.c	34 adev->reg_offset[GC_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in arct_reg_base_init() 35 adev->reg_offset[HDP_HWIP][i] = (uint32_t )(&(HDP_BASE.instance[i])); in arct_reg_base_init() 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t )(&(MMHUB_BASE.instance[i])); in arct_reg_base_init() 38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t )(&(NBIF0_BASE.instance[i])); in arct_reg_base_init() 39 adev->reg_offset[MP0_HWIP][i] = (uint32_t )(&(MP0_BASE.instance[i])); in arct_reg_base_init() 40 adev->reg_offset[MP1_HWIP][i] = (uint32_t )(&(MP1_BASE.instance[i])); in arct_reg_base_init() 41 adev->reg_offset[UVD_HWIP][i] = (uint32_t )(&(UVD_BASE.instance[i])); in arct_reg_base_init() 42 adev->reg_offset[DF_HWIP][i] = (uint32_t )(&(DF_BASE.instance[i])); in arct_reg_base_init() 53 adev->reg_offset[THM_HWIP][i] = (uint32_t )(&(THM_BASE.instance[i])); in arct_reg_base_init() 54 adev->reg_offset[UMC_HWIP][i] = (uint32_t )(&(UMC_BASE.instance[i])); in arct_reg_base_init() [all …]
H A D	aldebaran_reg_init.c	34 adev->reg_offset[GC_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in aldebaran_reg_base_init() 35 adev->reg_offset[HDP_HWIP][i] = (uint32_t )(&(HDP_BASE.instance[i])); in aldebaran_reg_base_init() 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t )(&(MMHUB_BASE.instance[i])); in aldebaran_reg_base_init() 37 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t )(&(ATHUB_BASE.instance[i])); in aldebaran_reg_base_init() 38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t )(&(NBIO_BASE.instance[i])); in aldebaran_reg_base_init() 39 adev->reg_offset[MP0_HWIP][i] = (uint32_t )(&(MP0_BASE.instance[i])); in aldebaran_reg_base_init() 40 adev->reg_offset[MP1_HWIP][i] = (uint32_t )(&(MP1_BASE.instance[i])); in aldebaran_reg_base_init() 41 adev->reg_offset[DF_HWIP][i] = (uint32_t )(&(DF_BASE.instance[i])); in aldebaran_reg_base_init() 49 adev->reg_offset[THM_HWIP][i] = (uint32_t )(&(THM_BASE.instance[i])); in aldebaran_reg_base_init() 50 adev->reg_offset[UMC_HWIP][i] = (uint32_t )(&(UMC_BASE.instance[i])); in aldebaran_reg_base_init() [all …]
H A D	sienna_cichlid_reg_init.c	35 adev->reg_offset[GC_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in sienna_cichlid_reg_base_init() 36 adev->reg_offset[HDP_HWIP][i] = (uint32_t )(&(HDP_BASE.instance[i])); in sienna_cichlid_reg_base_init() 40 adev->reg_offset[MP0_HWIP][i] = (uint32_t )(&(MP0_BASE.instance[i])); in sienna_cichlid_reg_base_init() 41 adev->reg_offset[MP1_HWIP][i] = (uint32_t )(&(MP1_BASE.instance[i])); in sienna_cichlid_reg_base_init() 42 adev->reg_offset[VCN_HWIP][i] = (uint32_t )(&(VCN_BASE.instance[i])); in sienna_cichlid_reg_base_init() 43 adev->reg_offset[DF_HWIP][i] = (uint32_t )(&(DF_BASE.instance[i])); in sienna_cichlid_reg_base_init() 44 adev->reg_offset[DCE_HWIP][i] = (uint32_t )(&(DCN_BASE.instance[i])); in sienna_cichlid_reg_base_init() 46 adev->reg_offset[SDMA0_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in sienna_cichlid_reg_base_init() 47 adev->reg_offset[SDMA1_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in sienna_cichlid_reg_base_init() 48 adev->reg_offset[SDMA2_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in sienna_cichlid_reg_base_init() [all …]
H A D	dimgrey_cavefish_reg_init.c	35 adev->reg_offset[GC_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in dimgrey_cavefish_reg_base_init() 36 adev->reg_offset[HDP_HWIP][i] = (uint32_t )(&(HDP_BASE.instance[i])); in dimgrey_cavefish_reg_base_init() 40 adev->reg_offset[MP0_HWIP][i] = (uint32_t )(&(MP0_BASE.instance[i])); in dimgrey_cavefish_reg_base_init() 41 adev->reg_offset[MP1_HWIP][i] = (uint32_t )(&(MP1_BASE.instance[i])); in dimgrey_cavefish_reg_base_init() 42 adev->reg_offset[VCN_HWIP][i] = (uint32_t )(&(VCN0_BASE.instance[i])); in dimgrey_cavefish_reg_base_init() 43 adev->reg_offset[DF_HWIP][i] = (uint32_t )(&(DF_BASE.instance[i])); in dimgrey_cavefish_reg_base_init() 44 adev->reg_offset[DCE_HWIP][i] = (uint32_t )(&(DCN_BASE.instance[i])); in dimgrey_cavefish_reg_base_init() 46 adev->reg_offset[SDMA0_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in dimgrey_cavefish_reg_base_init() 47 adev->reg_offset[SDMA1_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in dimgrey_cavefish_reg_base_init() 48 adev->reg_offset[SDMA2_HWIP][i] = (uint32_t )(&(GC_BASE.instance[i])); in dimgrey_cavefish_reg_base_init() [all …]

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