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Searched refs:regi_addr (Results 1 – 3 of 3) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/io_port2/
H A Dpcie_dma_ctrl.v21 `define EXTRACT_CHAN_NUM(reg_addr) regi_addr[`BIT_WIDTH(NUM_STREAMS)+DMA_REG_GRP_W-1:DMA_REG_GRP_W]
69 wire [19:0] regi_addr; net
75 .address(regi_addr), .data(regi_payload)
99 if (regi_addr == `GET_REG_OFFSET(DMA_CTRL_STATUS_REG, i)) begin
102 end else if (regi_addr == `GET_REG_OFFSET(DMA_FSIZE_REG, i)) begin
112 … if (reset | (regi_tvalid && regi_wr && (regi_addr == `GET_REG_OFFSET(DMA_PKT_CNT_REG, i)))) begin
121 … if (reset | (regi_tvalid && regi_wr && (regi_addr == `GET_REG_OFFSET(DMA_SAMP_CNT_REG, i)))) begin
132 …(regi_addr[DMA_REG_GRP_W-1:0] == DMA_PKT_CNT_REG) ? pkt_count_mem[`EXTRACT_CHAN_NUM(regi_…
133 …(regi_addr[DMA_REG_GRP_W-1:0] == DMA_SAMP_CNT_REG) ? samp_count_mem[`EXTRACT_CHAN_NUM(regi_…
134 …(regi_addr[DMA_REG_GRP_W-1:0] == DMA_FSIZE_REG) ? frame_size_mem[`EXTRACT_CHAN_NUM(regi_…
[all …]
H A Dpcie_iop2_msg_arbiter.v78 wire [19:0] regi_addr; net
95 ((regi_addr & E0_MASK) == E0_ADDR) ? DEST_E0 : (
96 ((regi_addr & E1_MASK) == E1_ADDR) ? DEST_E1 : (
97 ((regi_addr & E2_MASK) == E2_ADDR) ? DEST_E2 : (
98 ((regi_addr & E3_MASK) == E3_ADDR) ? DEST_E3 : (
116 .message(regi_msg), .rd_response(regi_rc), .address(regi_addr));
H A Dpcie_basic_regs.v40 wire [19:0] regi_addr, regi_addr_local; net
46 .address(regi_addr), .data(regi_payload)
55 assign regi_addr_local = regi_addr & PCIE_REG_ADDR_MASK;