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Searched refs:reset_vec (Results 1 – 25 of 42) sorted by relevance

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/dports/emulators/qemu42/qemu-4.2.1/hw/riscv/
H A Dspike.c191 uint32_t reset_vec[8] = { in spike_board_init() local
208 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { in spike_board_init()
209 reset_vec[i] = cpu_to_le32(reset_vec[i]); in spike_board_init()
211 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), in spike_board_init()
280 uint32_t reset_vec[8] = { in spike_v1_10_0_board_init() local
297 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { in spike_v1_10_0_board_init()
298 reset_vec[i] = cpu_to_le32(reset_vec[i]); in spike_v1_10_0_board_init()
300 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), in spike_v1_10_0_board_init()
366 uint32_t reset_vec[8] = { in spike_v1_09_1_board_init() local
412 reset_vec[i] = cpu_to_le32(reset_vec[i]); in spike_v1_09_1_board_init()
[all …]
H A Dsifive_e.c101 uint32_t reset_vec[2] = { in riscv_sifive_e_init() local
107 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { in riscv_sifive_e_init()
108 reset_vec[i] = cpu_to_le32(reset_vec[i]); in riscv_sifive_e_init()
110 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), in riscv_sifive_e_init()
/dports/emulators/qemu-utils/qemu-4.2.1/hw/riscv/
H A Dspike.c191 uint32_t reset_vec[8] = { in spike_board_init() local
208 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { in spike_board_init()
209 reset_vec[i] = cpu_to_le32(reset_vec[i]); in spike_board_init()
211 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), in spike_board_init()
280 uint32_t reset_vec[8] = { in spike_v1_10_0_board_init() local
297 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { in spike_v1_10_0_board_init()
298 reset_vec[i] = cpu_to_le32(reset_vec[i]); in spike_v1_10_0_board_init()
300 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), in spike_v1_10_0_board_init()
366 uint32_t reset_vec[8] = { in spike_v1_09_1_board_init() local
412 reset_vec[i] = cpu_to_le32(reset_vec[i]); in spike_v1_09_1_board_init()
[all …]
H A Dsifive_e.c101 uint32_t reset_vec[2] = { in riscv_sifive_e_init() local
107 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { in riscv_sifive_e_init()
108 reset_vec[i] = cpu_to_le32(reset_vec[i]); in riscv_sifive_e_init()
110 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), in riscv_sifive_e_init()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/riscv/
H A Dspike.c191 uint32_t reset_vec[8] = { in spike_board_init() local
208 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { in spike_board_init()
209 reset_vec[i] = cpu_to_le32(reset_vec[i]); in spike_board_init()
211 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), in spike_board_init()
281 uint32_t reset_vec[8] = { in spike_v1_10_0_board_init() local
298 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { in spike_v1_10_0_board_init()
299 reset_vec[i] = cpu_to_le32(reset_vec[i]); in spike_v1_10_0_board_init()
301 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), in spike_v1_10_0_board_init()
368 uint32_t reset_vec[8] = { in spike_v1_09_1_board_init() local
414 reset_vec[i] = cpu_to_le32(reset_vec[i]); in spike_v1_09_1_board_init()
[all …]
H A Dsifive_e.c101 uint32_t reset_vec[2] = {
107 for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
108 reset_vec[i] = cpu_to_le32(reset_vec[i]);
110 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/riscv/
H A Dspike.c198 uint32_t reset_vec[8] = { in spike_board_init() local
215 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { in spike_board_init()
216 reset_vec[i] = cpu_to_le32(reset_vec[i]); in spike_board_init()
218 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), in spike_board_init()
288 uint32_t reset_vec[8] = { in spike_v1_10_0_board_init() local
305 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { in spike_v1_10_0_board_init()
306 reset_vec[i] = cpu_to_le32(reset_vec[i]); in spike_v1_10_0_board_init()
308 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), in spike_v1_10_0_board_init()
375 uint32_t reset_vec[8] = { in spike_v1_09_1_board_init() local
421 reset_vec[i] = cpu_to_le32(reset_vec[i]); in spike_v1_09_1_board_init()
[all …]
H A Dsifive_e.c101 uint32_t reset_vec[2] = { in riscv_sifive_e_init() local
107 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { in riscv_sifive_e_init()
108 reset_vec[i] = cpu_to_le32(reset_vec[i]); in riscv_sifive_e_init()
110 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), in riscv_sifive_e_init()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/riscv/
H A Dspike.c203 uint32_t reset_vec[8] = { in spike_v1_10_0_board_init() local
220 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { in spike_v1_10_0_board_init()
221 reset_vec[i] = cpu_to_le32(reset_vec[i]); in spike_v1_10_0_board_init()
223 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), in spike_v1_10_0_board_init()
228 memmap[SPIKE_MROM].size - sizeof(reset_vec)) { in spike_v1_10_0_board_init()
234 memmap[SPIKE_MROM].base + sizeof(reset_vec), in spike_v1_10_0_board_init()
282 uint32_t reset_vec[8] = { in spike_v1_09_1_board_init() local
329 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { in spike_v1_09_1_board_init()
330 reset_vec[i] = cpu_to_le32(reset_vec[i]); in spike_v1_09_1_board_init()
332 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), in spike_v1_09_1_board_init()
[all …]
H A Dsifive_e.c121 uint32_t reset_vec[2] = { in riscv_sifive_e_init() local
127 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { in riscv_sifive_e_init()
128 reset_vec[i] = cpu_to_le32(reset_vec[i]); in riscv_sifive_e_init()
130 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), in riscv_sifive_e_init()
/dports/emulators/qemu60/qemu-6.0.0/hw/riscv/
H A Dboot.c261 uint32_t reset_vec[10] = { in riscv_setup_rom_reset_vec() local
275 reset_vec[3] = 0x0202a583; /* lw a1, 32(t0) */ in riscv_setup_rom_reset_vec()
276 reset_vec[4] = 0x0182a283; /* lw t0, 24(t0) */ in riscv_setup_rom_reset_vec()
278 reset_vec[3] = 0x0202b583; /* ld a1, 32(t0) */ in riscv_setup_rom_reset_vec()
279 reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */ in riscv_setup_rom_reset_vec()
283 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { in riscv_setup_rom_reset_vec()
284 reset_vec[i] = cpu_to_le32(reset_vec[i]); in riscv_setup_rom_reset_vec()
286 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), in riscv_setup_rom_reset_vec()
288 riscv_rom_copy_firmware_info(machine, rom_base, rom_size, sizeof(reset_vec), in riscv_setup_rom_reset_vec()
H A Dsifive_e.c95 uint32_t reset_vec[4]; in sifive_e_machine_init() local
98 reset_vec[1] = 0x200102b7; /* 0x1004: lui t0,0x20010 */ in sifive_e_machine_init()
100 reset_vec[1] = 0x204002b7; /* 0x1004: lui t0,0x20400 */ in sifive_e_machine_init()
102 reset_vec[2] = 0x00028067; /* 0x1008: jr t0 */ in sifive_e_machine_init()
104 reset_vec[0] = reset_vec[3] = 0; in sifive_e_machine_init()
107 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { in sifive_e_machine_init()
108 reset_vec[i] = cpu_to_le32(reset_vec[i]); in sifive_e_machine_init()
110 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), in sifive_e_machine_init()
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/riscv/
H A Dboot.c263 uint32_t reset_vec[10] = { in riscv_setup_rom_reset_vec() local
277 reset_vec[3] = 0x0202a583; /* lw a1, 32(t0) */ in riscv_setup_rom_reset_vec()
278 reset_vec[4] = 0x0182a283; /* lw t0, 24(t0) */ in riscv_setup_rom_reset_vec()
280 reset_vec[3] = 0x0202b583; /* ld a1, 32(t0) */ in riscv_setup_rom_reset_vec()
281 reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */ in riscv_setup_rom_reset_vec()
285 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { in riscv_setup_rom_reset_vec()
286 reset_vec[i] = cpu_to_le32(reset_vec[i]); in riscv_setup_rom_reset_vec()
288 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), in riscv_setup_rom_reset_vec()
290 riscv_rom_copy_firmware_info(machine, rom_base, rom_size, sizeof(reset_vec), in riscv_setup_rom_reset_vec()
H A Dsifive_e.c92 uint32_t reset_vec[4]; in sifive_e_machine_init() local
95 reset_vec[1] = 0x200102b7; /* 0x1004: lui t0,0x20010 */ in sifive_e_machine_init()
97 reset_vec[1] = 0x204002b7; /* 0x1004: lui t0,0x20400 */ in sifive_e_machine_init()
99 reset_vec[2] = 0x00028067; /* 0x1008: jr t0 */ in sifive_e_machine_init()
101 reset_vec[0] = reset_vec[3] = 0; in sifive_e_machine_init()
104 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { in sifive_e_machine_init()
105 reset_vec[i] = cpu_to_le32(reset_vec[i]); in sifive_e_machine_init()
107 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), in sifive_e_machine_init()
/dports/emulators/qemu/qemu-6.2.0/hw/riscv/
H A Dboot.c288 uint32_t reset_vec[10] = { in riscv_setup_rom_reset_vec() local
302 reset_vec[3] = 0x0202a583; /* lw a1, 32(t0) */ in riscv_setup_rom_reset_vec()
303 reset_vec[4] = 0x0182a283; /* lw t0, 24(t0) */ in riscv_setup_rom_reset_vec()
305 reset_vec[3] = 0x0202b583; /* ld a1, 32(t0) */ in riscv_setup_rom_reset_vec()
306 reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */ in riscv_setup_rom_reset_vec()
310 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { in riscv_setup_rom_reset_vec()
311 reset_vec[i] = cpu_to_le32(reset_vec[i]); in riscv_setup_rom_reset_vec()
313 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), in riscv_setup_rom_reset_vec()
315 riscv_rom_copy_firmware_info(machine, rom_base, rom_size, sizeof(reset_vec), in riscv_setup_rom_reset_vec()
H A Dsifive_e.c98 uint32_t reset_vec[4]; in sifive_e_machine_init() local
101 reset_vec[1] = 0x200102b7; /* 0x1004: lui t0,0x20010 */ in sifive_e_machine_init()
103 reset_vec[1] = 0x204002b7; /* 0x1004: lui t0,0x20400 */ in sifive_e_machine_init()
105 reset_vec[2] = 0x00028067; /* 0x1008: jr t0 */ in sifive_e_machine_init()
107 reset_vec[0] = reset_vec[3] = 0; in sifive_e_machine_init()
110 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { in sifive_e_machine_init()
111 reset_vec[i] = cpu_to_le32(reset_vec[i]); in sifive_e_machine_init()
113 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), in sifive_e_machine_init()
/dports/emulators/qemu5/qemu-5.2.0/hw/riscv/
H A Dsifive_e.c98 uint32_t reset_vec[4]; in sifive_e_machine_init() local
101 reset_vec[1] = 0x200102b7; /* 0x1004: lui t0,0x20010 */ in sifive_e_machine_init()
103 reset_vec[1] = 0x204002b7; /* 0x1004: lui t0,0x20400 */ in sifive_e_machine_init()
105 reset_vec[2] = 0x00028067; /* 0x1008: jr t0 */ in sifive_e_machine_init()
107 reset_vec[0] = reset_vec[3] = 0; in sifive_e_machine_init()
110 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { in sifive_e_machine_init()
111 reset_vec[i] = cpu_to_le32(reset_vec[i]); in sifive_e_machine_init()
113 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), in sifive_e_machine_init()
H A Dboot.c259 uint32_t reset_vec[10] = { in riscv_setup_rom_reset_vec() local
279 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { in riscv_setup_rom_reset_vec()
280 reset_vec[i] = cpu_to_le32(reset_vec[i]); in riscv_setup_rom_reset_vec()
282 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), in riscv_setup_rom_reset_vec()
284 riscv_rom_copy_firmware_info(rom_base, rom_size, sizeof(reset_vec), in riscv_setup_rom_reset_vec()
/dports/emulators/riscv-isa-sim/riscv-isa-sim-4f12984/riscv/
H A Dsim.cc307 uint32_t reset_vec[reset_vec_size] = { in set_rom() local
322 for (i = 0; reset_vec[i] != 0; i++) in set_rom()
323 reset_vec[i] = to_le(reset_vec[i]); in set_rom()
326 reset_vec[i] = to_be(reset_vec[i]); in set_rom()
330 std::swap(reset_vec[reset_vec_size-2], reset_vec[reset_vec_size-1]); in set_rom()
333 reset_vec[i] = to_le(reset_vec[i]); in set_rom()
336 std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec)); in set_rom()
/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/mips/netlogic/xlp/
H A Dsetup.c157 void *reset_vec; in prom_init() local
166 reset_vec = (void *)CKSEG1ADDR(RESET_VEC_PHYS); in prom_init()
167 memset(reset_vec, 0, RESET_VEC_SIZE); in prom_init()
168 memcpy(reset_vec, (void *)nlm_reset_entry, in prom_init()
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/mips/netlogic/xlp/
H A Dsetup.c157 void *reset_vec; in prom_init() local
166 reset_vec = (void *)CKSEG1ADDR(RESET_VEC_PHYS); in prom_init()
167 memset(reset_vec, 0, RESET_VEC_SIZE); in prom_init()
168 memcpy(reset_vec, (void *)nlm_reset_entry, in prom_init()
/dports/multimedia/libv4l/linux-5.13-rc2/arch/mips/netlogic/xlp/
H A Dsetup.c157 void *reset_vec; in prom_init() local
166 reset_vec = (void *)CKSEG1ADDR(RESET_VEC_PHYS); in prom_init()
167 memset(reset_vec, 0, RESET_VEC_SIZE); in prom_init()
168 memcpy(reset_vec, (void *)nlm_reset_entry, in prom_init()
/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/mips/netlogic/xlr/
H A Dsetup.c175 void *reset_vec; in prom_init() local
189 reset_vec = (void *)CKSEG1ADDR(RESET_VEC_PHYS); in prom_init()
190 memset(reset_vec, 0, RESET_VEC_SIZE); in prom_init()
191 memcpy(reset_vec, (void *)nlm_reset_entry, in prom_init()
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/mips/netlogic/xlr/
H A Dsetup.c175 void *reset_vec; in prom_init() local
189 reset_vec = (void *)CKSEG1ADDR(RESET_VEC_PHYS); in prom_init()
190 memset(reset_vec, 0, RESET_VEC_SIZE); in prom_init()
191 memcpy(reset_vec, (void *)nlm_reset_entry, in prom_init()
/dports/multimedia/libv4l/linux-5.13-rc2/arch/mips/netlogic/xlr/
H A Dsetup.c175 void *reset_vec; in prom_init() local
189 reset_vec = (void *)CKSEG1ADDR(RESET_VEC_PHYS); in prom_init()
190 memset(reset_vec, 0, RESET_VEC_SIZE); in prom_init()
191 memcpy(reset_vec, (void *)nlm_reset_entry, in prom_init()

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