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Searched refs:right_is_neg (Results 1 – 1 of 1) sorted by relevance

/dports/cad/iverilog/verilog-11.0/vvp/
H A Dvthread.cc3983 bool left_is_neg, bool right_is_neg) in do_verylong_mod() argument
4000 unsigned rb_carry = right_is_neg? 1 : 0; in do_verylong_mod()
4019 if (right_is_neg) { in do_verylong_mod()
4228 bool right_is_neg = valb.value(valb.size()-1) == BIT4_1; in of_MOD_S() local
4229 do_verylong_mod(vala, valb, left_is_neg, right_is_neg); in of_MOD_S()