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/dports/cad/verilator/verilator-4.216/test_regress/t/
H A Dt_reloop_cam.v120 logic [7:0] rwidx_d1r; register
132 rwidx_d1r <= rwidx;
161 entries[rwidx_d1r] <= '{valid:wdat_val_d1r, data:wdat_d1r};
172 rdat_d2r <= entries[rwidx_d1r].data;
173 rdat_val_d2r <= entries[rwidx_d1r].valid;